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* [PATCH] spi: nuc900: Fix setting multiple bits settings in register
@ 2014-03-21  5:24 Axel Lin
  2014-03-21  8:13 ` Geert Uytterhoeven
  2014-03-21 17:49 ` Mark Brown
  0 siblings, 2 replies; 4+ messages in thread
From: Axel Lin @ 2014-03-21  5:24 UTC (permalink / raw)
  To: Mark Brown; +Cc: Wan ZongShun, linux-spi-u79uwXL29TY76Z2rM5mHXA

The correct way to set multiple bits settings is always clear these
bit fields before set new settings.

Current code does not cause problem because the reset value of these
bit fields are 0, and these settings only set once during probe.

Signed-off-by: Axel Lin <axel.lin-8E1dMatC8ynQT0dZR+AlfA@public.gmane.org>
---
 drivers/spi/spi-nuc900.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/spi/spi-nuc900.c b/drivers/spi/spi-nuc900.c
index 675c210..16e30de 100644
--- a/drivers/spi/spi-nuc900.c
+++ b/drivers/spi/spi-nuc900.c
@@ -37,7 +37,9 @@
 /* usi register bit */
 #define ENINT		(0x01 << 17)
 #define ENFLG		(0x01 << 16)
+#define SLEEP		(0x0f << 12)
 #define TXNUM		(0x03 << 8)
+#define TXBITLEN	(0x1f << 3)
 #define TXNEG		(0x01 << 2)
 #define RXNEG		(0x01 << 1)
 #define LSB		(0x01 << 10)
@@ -115,19 +117,16 @@ static void nuc900_spi_chipsel(struct spi_device *spi, int value)
 	}
 }
 
-static void nuc900_spi_setup_txnum(struct nuc900_spi *hw,
-							unsigned int txnum)
+static void nuc900_spi_setup_txnum(struct nuc900_spi *hw, unsigned int txnum)
 {
 	unsigned int val;
 	unsigned long flags;
 
 	spin_lock_irqsave(&hw->lock, flags);
 
-	val = __raw_readl(hw->regs + USI_CNT);
+	val = __raw_readl(hw->regs + USI_CNT) & ~TXNUM;
 
-	if (!txnum)
-		val &= ~TXNUM;
-	else
+	if (txnum)
 		val |= txnum << 0x08;
 
 	__raw_writel(val, hw->regs + USI_CNT);
@@ -144,7 +143,7 @@ static void nuc900_spi_setup_txbitlen(struct nuc900_spi *hw,
 
 	spin_lock_irqsave(&hw->lock, flags);
 
-	val = __raw_readl(hw->regs + USI_CNT);
+	val = __raw_readl(hw->regs + USI_CNT) & ~TXBITLEN;
 
 	val |= (txbitlen << 0x03);
 
@@ -283,12 +282,11 @@ static void nuc900_set_sleep(struct nuc900_spi *hw, unsigned int sleep)
 
 	spin_lock_irqsave(&hw->lock, flags);
 
-	val = __raw_readl(hw->regs + USI_CNT);
+	val = __raw_readl(hw->regs + USI_CNT) & ~SLEEP;
 
 	if (sleep)
 		val |= (sleep << 12);
-	else
-		val &= ~(0x0f << 12);
+
 	__raw_writel(val, hw->regs + USI_CNT);
 
 	spin_unlock_irqrestore(&hw->lock, flags);
-- 
1.8.3.2



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^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH] spi: nuc900: Fix setting multiple bits settings in register
  2014-03-21  5:24 [PATCH] spi: nuc900: Fix setting multiple bits settings in register Axel Lin
@ 2014-03-21  8:13 ` Geert Uytterhoeven
       [not found]   ` <CAMuHMdVYHnv2PGaerL50PhK_a1E=LaEwdkhHNgyaqX=WO-FOXA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
  2014-03-21 17:49 ` Mark Brown
  1 sibling, 1 reply; 4+ messages in thread
From: Geert Uytterhoeven @ 2014-03-21  8:13 UTC (permalink / raw)
  To: Axel Lin; +Cc: Mark Brown, Wan ZongShun, linux-spi

Hi Axel,

On Fri, Mar 21, 2014 at 6:24 AM, Axel Lin <axel.lin-8E1dMatC8ynQT0dZR+AlfA@public.gmane.org> wrote:
> -       val = __raw_readl(hw->regs + USI_CNT);
> +       val = __raw_readl(hw->regs + USI_CNT) & ~TXNUM;
>
> -       if (!txnum)
> -               val &= ~TXNUM;
> -       else
> +       if (txnum)
>                 val |= txnum << 0x08;

I think it's easier to read if you keep the masking and setting together,
and remove the conditional, e.g.

        val = __raw_readl(hw->regs + USI_CNT);
        val = (val & ~TXNUM) | (txnum << 0x08);
        __raw_writel(val, hw->regs + USI_CNT);

Just my personal thoughts, too.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] spi: nuc900: Fix setting multiple bits settings in register
       [not found]   ` <CAMuHMdVYHnv2PGaerL50PhK_a1E=LaEwdkhHNgyaqX=WO-FOXA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2014-03-21 12:08     ` Mark Brown
  0 siblings, 0 replies; 4+ messages in thread
From: Mark Brown @ 2014-03-21 12:08 UTC (permalink / raw)
  To: Geert Uytterhoeven; +Cc: Axel Lin, Wan ZongShun, linux-spi

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On Fri, Mar 21, 2014 at 09:13:00AM +0100, Geert Uytterhoeven wrote:

> I think it's easier to read if you keep the masking and setting together,
> and remove the conditional, e.g.

>         val = __raw_readl(hw->regs + USI_CNT);
>         val = (val & ~TXNUM) | (txnum << 0x08);
>         __raw_writel(val, hw->regs + USI_CNT);

> Just my personal thoughts, too.

I agree, that seems clearer.

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^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] spi: nuc900: Fix setting multiple bits settings in register
  2014-03-21  5:24 [PATCH] spi: nuc900: Fix setting multiple bits settings in register Axel Lin
  2014-03-21  8:13 ` Geert Uytterhoeven
@ 2014-03-21 17:49 ` Mark Brown
  1 sibling, 0 replies; 4+ messages in thread
From: Mark Brown @ 2014-03-21 17:49 UTC (permalink / raw)
  To: Axel Lin; +Cc: Wan ZongShun, linux-spi-u79uwXL29TY76Z2rM5mHXA

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On Fri, Mar 21, 2014 at 01:24:14PM +0800, Axel Lin wrote:
> The correct way to set multiple bits settings is always clear these
> bit fields before set new settings.

Applied, thanks.

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^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2014-03-21 17:49 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-03-21  5:24 [PATCH] spi: nuc900: Fix setting multiple bits settings in register Axel Lin
2014-03-21  8:13 ` Geert Uytterhoeven
     [not found]   ` <CAMuHMdVYHnv2PGaerL50PhK_a1E=LaEwdkhHNgyaqX=WO-FOXA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-03-21 12:08     ` Mark Brown
2014-03-21 17:49 ` Mark Brown

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