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From: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
To: Vinod Koul <vinod.koul-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
	Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	dmaengine-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: Andy Shevchenko
	<andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
Subject: [PATCH v2 2/9] spi: dw-mid: clear BUSY flag fist and test other one
Date: Mon,  2 Mar 2015 20:15:59 +0200	[thread overview]
Message-ID: <1425320166-13788-3-git-send-email-andriy.shevchenko@linux.intel.com> (raw)
In-Reply-To: <1425320166-13788-1-git-send-email-andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>

The logic of DMA completion is broken now since test_and_clear_bit() never
returns the other bit is set. It means condition are always false and we have
spi_finalize_current_transfer() called per each DMA completion which is wrong.

The patch fixes logic by clearing BUSY bit first and then check for the other
one.

Fixes: 30c8eb52cc4a (spi: dw-mid: split rx and tx callbacks when DMA)
Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
---
 drivers/spi/spi-dw-mid.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index a8a5ee3..c8416ef 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -108,7 +108,8 @@ static void dw_spi_dma_tx_done(void *arg)
 {
 	struct dw_spi *dws = arg;
 
-	if (test_and_clear_bit(TX_BUSY, &dws->dma_chan_busy) & BIT(RX_BUSY))
+	clear_bit(TX_BUSY, &dws->dma_chan_busy);
+	if (test_bit(RX_BUSY, &dws->dma_chan_busy))
 		return;
 	spi_finalize_current_transfer(dws->master);
 }
@@ -156,7 +157,8 @@ static void dw_spi_dma_rx_done(void *arg)
 {
 	struct dw_spi *dws = arg;
 
-	if (test_and_clear_bit(RX_BUSY, &dws->dma_chan_busy) & BIT(TX_BUSY))
+	clear_bit(RX_BUSY, &dws->dma_chan_busy);
+	if (test_bit(TX_BUSY, &dws->dma_chan_busy))
 		return;
 	spi_finalize_current_transfer(dws->master);
 }
-- 
2.1.4

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  parent reply	other threads:[~2015-03-02 18:15 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-02 18:15 [PATCH v2 0/9] spi: dw: make DMA working Andy Shevchenko
     [not found] ` <1425320166-13788-1-git-send-email-andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2015-03-02 18:15   ` [PATCH v2 1/9] spi: dw-mid: avoid potential NULL dereference Andy Shevchenko
     [not found]     ` <1425320166-13788-2-git-send-email-andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2015-03-06 11:28       ` Mark Brown
     [not found]         ` <20150306112858.GI21293-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2015-03-06 12:53           ` Andy Shevchenko
2015-03-02 18:15   ` Andy Shevchenko [this message]
     [not found]     ` <1425320166-13788-3-git-send-email-andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2015-03-06 11:25       ` [PATCH v2 2/9] spi: dw-mid: clear BUSY flag fist and test other one Mark Brown
     [not found]         ` <20150306112519.GH21293-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2015-03-06 12:40           ` Andy Shevchenko
     [not found]             ` <1425645629.14897.196.camel-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2015-03-07 11:04               ` Mark Brown
2015-03-02 18:16   ` [PATCH v2 3/9] spi: dw-mid: convert value of dma_width to enum dma_slave_buswidth Andy Shevchenko
2015-03-02 18:16   ` [PATCH v2 4/9] spi: dw-mid: split dma_setup() from dma_transfer() Andy Shevchenko
2015-03-02 18:16   ` [PATCH v2 5/9] spi: dw-mid: take care of FIFO overrun/underrun when do DMA Andy Shevchenko
2015-03-02 18:16   ` [PATCH v2 6/9] spi: dw-mid: clear ongoing DMA transfers on timeout Andy Shevchenko
2015-03-02 18:16   ` [PATCH v2 7/9] spi: dw-mid: move to use core SPI DMA mappings Andy Shevchenko
2015-03-02 18:16   ` [PATCH v2 8/9] spi: dw-mid: convert to use dw_dmac instead of intel_mid_dma Andy Shevchenko
2015-03-02 18:16   ` [PATCH v2 9/9] dmaengine: intel-mid-dma: remove the driver Andy Shevchenko

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