Re: [RFC/PATCH 0/2] spi: spi-dw: Select 16b or 32b register access

[Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>]

On Wed, 2015-03-04 at 14:31 -0600, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> 
> The Altera Arria10 SoC requires 32 bit accesses to peripherals. The
> DesignWare SPI peripheral registers are on 32bit boundaries so this
> patch is minimal. Function pointers are used to select 32bit access
> or 16bit accesses.


So, what is exactly the issue when we read only half of the register?
Bus lock, or what?

> 
> Thor Thayer (2):
>   dt-binding: spi: spi-dw: Select 16b or 32b access for Designware SPI
>   spi: dw-spi: Pointers select 16b vs. 32b DesignWare access
> 
>  Documentation/devicetree/bindings/spi/spi-dw.txt |    1 +
>  drivers/spi/spi-dw-mmio.c                        |    7 +++-
>  drivers/spi/spi-dw.c                             |   38 +++++++++++++---------
>  drivers/spi/spi-dw.h                             |   10 +++---
>  4 files changed, 35 insertions(+), 21 deletions(-)
> 


-- 
Andy Shevchenko <andriy.shevchenko-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Intel Finland Oy

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