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Subject: [PATCHv3] spi: dw-spi: Convert to 32-bit register accesses
Date: Wed, 11 Mar 2015 14:20:43 -0500 [thread overview]
Message-ID: <1426101644-5816-1-git-send-email-tthayer@opensource.altera.com> (raw)
From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
Altera's Arria10 SoC requires all write accesses of APB peripherals
are 32-bit. The DesignWare documentation indicates this change
is acceptable.
Request for Testing:
Please test on legacy DesignWare SPI devices. If a problem is
discovered, please reply to this thread.
Additional Documentation To Support this Change:
The DesignWare documentation DW_apb_ssi databook states:
All registers in the DW_apb_ssi are addressed on 32-bit boundaries
to remain consistent with the AHB bus. Where the physical size of
any register is less than 32-bits wide, the upper unused bits of the
32-bit boundary are reserved. Writing to these bits has no effect,
reading from these bits returns 0. [1]
Tested On:
Altera CycloneV Development Kit
Altera Arria10 Development Kit
[1] Section 6.1 of dw_apb_ssi.pdf (version 3.22a)
Thor Thayer (1):
spi: dw-spi: Convert 16bit accesses to 32bit accesses
drivers/spi/spi-dw.c | 34 +++++++++++++++++-----------------
drivers/spi/spi-dw.h | 10 ----------
2 files changed, 17 insertions(+), 27 deletions(-)
--
1.7.9.5
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next reply other threads:[~2015-03-11 19:20 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-11 19:20 tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx [this message]
[not found] ` <1426101644-5816-1-git-send-email-tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
2015-03-11 19:20 ` [PATCHv3] spi: dw-spi: Convert 16bit accesses to 32bit accesses tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx
[not found] ` <1426101644-5816-2-git-send-email-tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
2015-03-11 19:28 ` Andy Shevchenko
[not found] ` <1426102087.14897.279.camel-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2015-03-11 21:11 ` Thor Thayer
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