[PATCH 00/28] MIPS Boston board support

[PATCH 00/28] MIPS Boston board support

[Paul Burton]

This series introduces support for the Imagination Technologies MIPS
Boston development board. Boston is an FPGA-based development board
akin to the much older Malta board, built around a Xilinx FPGA running
a MIPS CPU & other logic including a PCIe root port connected to an
Intel EG20T Platform Controller Hub. This provides a base set of
peripherals including SATA, USB, SD/MMC, ethernet, I2C & GPIOs. PCIe
slots are also present for expansion.

Paul Burton (28):
  serial: earlycon: allow MEM32 I/O for DT earlycon
  dt-bindings: ascii-lcd: Document a binding for simple ASCII LCDs
  auxdisplay: driver for simple memory mapped ASCII LCD displays
  MIPS: PCI: compatibility with ARM-like PCI host drivers
  PCI: xilinx: keep references to both IRQ domains
  PCI: xilinx: unify INTx & MSI interrupt FIFO decode
  PCI: xilinx: always clear interrupt decode register
  PCI: xilinx: fix INTX irq dispatch
  PCI: xilinx: allow build on MIPS platforms
  misc: pch_phub: allow build on MIPS platforms
  dmaengine: pch_dma: allow build on MIPS platforms
  gpio: pch: allow build on MIPS platforms
  gpio: pch: allow use from device tree
  i2c: eg20t: allow build on MIPS platforms
  i2c: eg20t: set i2c_adapter->dev.of_node
  rtc: m41t80: add devicetree probe support
  spi: topcliff-pch: allow build for MIPS platforms
  ptp: pch: allow build on MIPS platforms
  net: pch_gbe: allow build on MIPS platforms
  net: pch_gbe: clear interrupt FIFO during probe
  net: pch_gbe: mark Minnow PHY reset GPIO active low
  net: pch_gbe: pull PHY GPIO handling out of Minnow code
  net: pch_gbe: always reset PHY along with MAC
  net: pch_gbe: add device tree support
  net: pch_gbe: allow longer for resets
  MIPS: support for generating FIT (.itb) images
  dt-bindings: mips: img,boston: Document img,boston binding
  MIPS: Boston board support

 Documentation/devicetree/bindings/ascii-lcd.txt    |  10 +
 .../devicetree/bindings/mips/img/boston.txt        |  15 ++
 MAINTAINERS                                        |  14 ++
 arch/mips/Kbuild.platforms                         |   1 +
 arch/mips/Kconfig                                  |  45 ++++
 arch/mips/Makefile                                 |   6 +-
 arch/mips/boot/Makefile                            |  61 ++++++
 arch/mips/boot/dts/Makefile                        |   1 +
 arch/mips/boot/dts/img/Makefile                    |   7 +
 arch/mips/boot/dts/img/boston.dts                  | 201 ++++++++++++++++++
 arch/mips/boot/skeleton.its                        |  24 +++
 arch/mips/boston/Makefile                          |  12 ++
 arch/mips/boston/Platform                          |   8 +
 arch/mips/boston/init.c                            |  75 +++++++
 arch/mips/boston/int.c                             |  33 +++
 arch/mips/boston/time.c                            |  89 ++++++++
 arch/mips/boston/vmlinux.its                       |  23 ++
 arch/mips/configs/boston_defconfig                 | 170 +++++++++++++++
 .../asm/mach-boston/cpu-feature-overrides.h        |  26 +++
 arch/mips/include/asm/mach-boston/irq.h            |  18 ++
 arch/mips/include/asm/mach-boston/spaces.h         |  20 ++
 arch/mips/include/asm/pci.h                        |  67 +++++-
 arch/mips/lib/iomap-pci.c                          |   2 +-
 arch/mips/pci/Makefile                             |   6 +
 arch/mips/pci/pci-generic.c                        | 138 ++++++++++++
 arch/mips/pci/pci-legacy.c                         | 232 +++++++++++++++++++++
 arch/mips/pci/pci.c                                | 226 +-------------------
 drivers/auxdisplay/Kconfig                         |   7 +
 drivers/auxdisplay/Makefile                        |   1 +
 drivers/auxdisplay/ascii-lcd.c                     | 230 ++++++++++++++++++++
 drivers/dma/Kconfig                                |   2 +-
 drivers/gpio/Kconfig                               |   2 +-
 drivers/gpio/gpio-pch.c                            |   1 +
 drivers/i2c/busses/Kconfig                         |   2 +-
 drivers/i2c/busses/i2c-eg20t.c                     |   1 +
 drivers/misc/Kconfig                               |   2 +-
 drivers/net/ethernet/oki-semi/pch_gbe/Kconfig      |   2 +-
 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h    |   4 +-
 .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c   |  74 +++++--
 drivers/of/fdt.c                                   |   2 +-
 drivers/pci/host/Kconfig                           |   2 +-
 drivers/pci/host/pcie-xilinx.c                     | 123 +++++------
 drivers/ptp/Kconfig                                |   2 +-
 drivers/rtc/rtc-m41t80.c                           |  26 +++
 drivers/spi/Kconfig                                |   2 +-
 drivers/tty/serial/Makefile                        |   1 +
 drivers/tty/serial/earlycon.c                      |  15 +-
 include/linux/serial_core.h                        |   2 +-
 48 files changed, 1720 insertions(+), 313 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/ascii-lcd.txt
 create mode 100644 Documentation/devicetree/bindings/mips/img/boston.txt
 create mode 100644 arch/mips/boot/dts/img/Makefile
 create mode 100644 arch/mips/boot/dts/img/boston.dts
 create mode 100644 arch/mips/boot/skeleton.its
 create mode 100644 arch/mips/boston/Makefile
 create mode 100644 arch/mips/boston/Platform
 create mode 100644 arch/mips/boston/init.c
 create mode 100644 arch/mips/boston/int.c
 create mode 100644 arch/mips/boston/time.c
 create mode 100644 arch/mips/boston/vmlinux.its
 create mode 100644 arch/mips/configs/boston_defconfig
 create mode 100644 arch/mips/include/asm/mach-boston/cpu-feature-overrides.h
 create mode 100644 arch/mips/include/asm/mach-boston/irq.h
 create mode 100644 arch/mips/include/asm/mach-boston/spaces.h
 create mode 100644 arch/mips/pci/pci-generic.c
 create mode 100644 arch/mips/pci/pci-legacy.c
 create mode 100644 drivers/auxdisplay/ascii-lcd.c

-- 
2.6.2

[PATCH 17/28] spi: topcliff-pch: allow build for MIPS platforms

[Paul Burton]

Allow the topcliff-pch driver to be built for MIPS platforms, in
preparation for use on the MIPS Boston board.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/spi/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 8b9c2a3..7c78d52 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -585,7 +585,7 @@ config SPI_TEGRA20_SLINK
 
 config SPI_TOPCLIFF_PCH
 	tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) SPI"
-	depends on PCI && (X86_32 || COMPILE_TEST)
+	depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
 	help
 	  SPI driver for the Topcliff PCH (Platform Controller Hub) SPI bus
 	  used in some x86 embedded processors.
-- 
2.6.2

Re: [PATCH 00/28] MIPS Boston board support

[Mark Brown]

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On Mon, Nov 30, 2015 at 04:21:25PM +0000, Paul Burton wrote:
> This series introduces support for the Imagination Technologies MIPS
> Boston development board. Boston is an FPGA-based development board
> akin to the much older Malta board, built around a Xilinx FPGA running
> a MIPS CPU & other logic including a PCIe root port connected to an
> Intel EG20T Platform Controller Hub. This provides a base set of
> peripherals including SATA, USB, SD/MMC, ethernet, I2C & GPIOs. PCIe
> slots are also present for expansion.

This is an insanely big CC list :(

What are the interdependencies here - does this really need to be one
patch series or can the individual driver changes go in separately?  The
latter is more normal, usually rather than a single patch series we just
have each driver sent by itself since that's usually easier to handle
and avoids the massive CC lists.

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Applied "spi: topcliff-pch: allow build for MIPS platforms" to the spi tree

[Mark Brown]

The patch

   spi: topcliff-pch: allow build for MIPS platforms

has been applied to the spi tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From f05ca854b3df79bf6596de5102eb99ca10d6089f Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
Date: Mon, 30 Nov 2015 16:21:42 +0000
Subject: [PATCH] spi: topcliff-pch: allow build for MIPS platforms

Allow the topcliff-pch driver to be built for MIPS platforms, in
preparation for use on the MIPS Boston board.

Signed-off-by: Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
Signed-off-by: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
 drivers/spi/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 8b9c2a38d1cc..7c78d52591af 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -585,7 +585,7 @@ config SPI_TEGRA20_SLINK
 
 config SPI_TOPCLIFF_PCH
 	tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) SPI"
-	depends on PCI && (X86_32 || COMPILE_TEST)
+	depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
 	help
 	  SPI driver for the Topcliff PCH (Platform Controller Hub) SPI bus
 	  used in some x86 embedded processors.
-- 
2.6.2

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Re: [PATCH 00/28] MIPS Boston board support

[Linus Walleij]

On Mon, Nov 30, 2015 at 5:34 PM, Mark Brown <broonie@kernel.org> wrote:
> On Mon, Nov 30, 2015 at 04:21:25PM +0000, Paul Burton wrote:
>> This series introduces support for the Imagination Technologies MIPS
>> Boston development board. Boston is an FPGA-based development board
>> akin to the much older Malta board, built around a Xilinx FPGA running
>> a MIPS CPU & other logic including a PCIe root port connected to an
>> Intel EG20T Platform Controller Hub. This provides a base set of
>> peripherals including SATA, USB, SD/MMC, ethernet, I2C & GPIOs. PCIe
>> slots are also present for expansion.
>
> This is an insanely big CC list :(
>
> What are the interdependencies here - does this really need to be one
> patch series or can the individual driver changes go in separately?

I took the two GPIO patches and ran off with them at least.

Yours,
Linus Walleij