* [PATCH v2 0/2] add mt7622 spi support
@ 2017-06-10 4:46 Leilk Liu
[not found] ` <1497069989-30584-1-git-send-email-leilk.liu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2017-06-10 4:46 ` [PATCH v2 2/2] spi: mediatek: add spi support for mt7622 IC Leilk Liu
0 siblings, 2 replies; 5+ messages in thread
From: Leilk Liu @ 2017-06-10 4:46 UTC (permalink / raw)
To: Mark Brown
Cc: Mark Rutland, Matthias Brugger, Sascha Hauer,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-spi-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
sean.wang-NuS5LvNUpcJWk0Htik3J/w
This series are based on 4.12-rc1 and provide 2 patches to support mt7622 IC.
Change in v2:
1. rename patch title;
2. use enhance_timing to instead of adjust_reg.
Change in v1:
1. update document to add mt7622;
2. add adjust register define support;
3. add mt7622_compat.
Leilk Liu (2):
spi: mediatek: adjust register to enhance time accuracy
spi: mediatek: add spi support for mt7622 IC
drivers/spi/spi-mt65xx.c | 54 +++++++++++++++++++++++++++---
include/linux/platform_data/spi-mt65xx.h | 2 ++
2 files changed, 51 insertions(+), 5 deletions(-)
--
1.7.9.5
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^ permalink raw reply [flat|nested] 5+ messages in thread[parent not found: <1497069989-30584-1-git-send-email-leilk.liu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>]
* [PATCH v2 1/2] spi: mediatek: adjust register to enhance time accuracy [not found] ` <1497069989-30584-1-git-send-email-leilk.liu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> @ 2017-06-10 4:46 ` Leilk Liu 2017-06-13 21:09 ` Applied "spi: mediatek: adjust register to enhance time accuracy" to the spi tree Mark Brown 0 siblings, 1 reply; 5+ messages in thread From: Leilk Liu @ 2017-06-10 4:46 UTC (permalink / raw) To: Mark Brown Cc: Mark Rutland, Matthias Brugger, Sascha Hauer, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-spi-u79uwXL29TY76Z2rM5mHXA, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, sean.wang-NuS5LvNUpcJWk0Htik3J/w, Leilk Liu this patch adjust register to enhance time accuracy. Signed-off-by: Leilk Liu <leilk.liu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> --- drivers/spi/spi-mt65xx.c | 45 ++++++++++++++++++++++++++---- include/linux/platform_data/spi-mt65xx.h | 2 ++ 2 files changed, 42 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index 278867a..eae73b5 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -35,11 +35,15 @@ #define SPI_CMD_REG 0x0018 #define SPI_STATUS0_REG 0x001c #define SPI_PAD_SEL_REG 0x0024 +#define SPI_CFG2_REG 0x0028 #define SPI_CFG0_SCK_HIGH_OFFSET 0 #define SPI_CFG0_SCK_LOW_OFFSET 8 #define SPI_CFG0_CS_HOLD_OFFSET 16 #define SPI_CFG0_CS_SETUP_OFFSET 24 +#define SPI_ADJUST_CFG0_SCK_LOW_OFFSET 16 +#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0 +#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16 #define SPI_CFG1_CS_IDLE_OFFSET 0 #define SPI_CFG1_PACKET_LOOP_OFFSET 8 @@ -55,6 +59,8 @@ #define SPI_CMD_RST BIT(2) #define SPI_CMD_PAUSE_EN BIT(4) #define SPI_CMD_DEASSERT BIT(5) +#define SPI_CMD_SAMPLE_SEL BIT(6) +#define SPI_CMD_CS_POL BIT(7) #define SPI_CMD_CPHA BIT(8) #define SPI_CMD_CPOL BIT(9) #define SPI_CMD_RX_DMA BIT(10) @@ -80,6 +86,8 @@ struct mtk_spi_compatible { bool need_pad_sel; /* Must explicitly send dummy Tx bytes to do Rx only transfer */ bool must_tx; + /* some IC design adjust cfg register to enhance time accuracy */ + bool enhance_timing; }; struct mtk_spi { @@ -108,6 +116,8 @@ struct mtk_spi { static const struct mtk_chip_config mtk_default_chip_info = { .rx_mlsb = 1, .tx_mlsb = 1, + .cs_pol = 0, + .sample_sel = 0, }; static const struct of_device_id mtk_spi_of_match[] = { @@ -182,6 +192,17 @@ static int mtk_spi_prepare_message(struct spi_master *master, reg_val |= SPI_CMD_RX_ENDIAN; #endif + if (mdata->dev_comp->enhance_timing) { + if (chip_config->cs_pol) + reg_val |= SPI_CMD_CS_POL; + else + reg_val &= ~SPI_CMD_CS_POL; + if (chip_config->sample_sel) + reg_val |= SPI_CMD_SAMPLE_SEL; + else + reg_val &= ~SPI_CMD_SAMPLE_SEL; + } + /* set finish and pause interrupt always enable */ reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE; @@ -233,11 +254,25 @@ static void mtk_spi_prepare_transfer(struct spi_master *master, sck_time = (div + 1) / 2; cs_time = sck_time * 2; - reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET); - reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); - reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); - reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET); - writel(reg_val, mdata->base + SPI_CFG0_REG); + if (mdata->dev_comp->enhance_timing) { + reg_val |= (((sck_time - 1) & 0xffff) + << SPI_CFG0_SCK_HIGH_OFFSET); + reg_val |= (((sck_time - 1) & 0xffff) + << SPI_ADJUST_CFG0_SCK_LOW_OFFSET); + writel(reg_val, mdata->base + SPI_CFG2_REG); + reg_val |= (((cs_time - 1) & 0xffff) + << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); + reg_val |= (((cs_time - 1) & 0xffff) + << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); + writel(reg_val, mdata->base + SPI_CFG0_REG); + } else { + reg_val |= (((sck_time - 1) & 0xff) + << SPI_CFG0_SCK_HIGH_OFFSET); + reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); + reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); + reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET); + writel(reg_val, mdata->base + SPI_CFG0_REG); + } reg_val = readl(mdata->base + SPI_CFG1_REG); reg_val &= ~SPI_CFG1_CS_IDLE_MASK; diff --git a/include/linux/platform_data/spi-mt65xx.h b/include/linux/platform_data/spi-mt65xx.h index 54b0448..ba4e4bb 100644 --- a/include/linux/platform_data/spi-mt65xx.h +++ b/include/linux/platform_data/spi-mt65xx.h @@ -16,5 +16,7 @@ struct mtk_chip_config { u32 tx_mlsb; u32 rx_mlsb; + u32 cs_pol; + u32 sample_sel; }; #endif -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Applied "spi: mediatek: adjust register to enhance time accuracy" to the spi tree 2017-06-10 4:46 ` [PATCH v2 1/2] spi: mediatek: adjust register to enhance time accuracy Leilk Liu @ 2017-06-13 21:09 ` Mark Brown 0 siblings, 0 replies; 5+ messages in thread From: Mark Brown @ 2017-06-13 21:09 UTC (permalink / raw) To: Leilk Liu Cc: Mark Rutland, devicetree, Sascha Hauer, sean.wang, linux-kernel, linux-spi, Mark Brown, linux-mediatek, Matthias Brugger, linux-arm-kernel The patch spi: mediatek: adjust register to enhance time accuracy has been applied to the spi tree at git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >From 058fe49da3b6ab71b57effd49dcc5d007071eea5 Mon Sep 17 00:00:00 2001 From: Leilk Liu <leilk.liu@mediatek.com> Date: Mon, 12 Jun 2017 09:24:39 +0800 Subject: [PATCH] spi: mediatek: adjust register to enhance time accuracy this patch adjust register to enhance time accuracy. Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> Signed-off-by: Mark Brown <broonie@kernel.org> --- drivers/spi/spi-mt65xx.c | 45 ++++++++++++++++++++++++++++---- include/linux/platform_data/spi-mt65xx.h | 2 ++ 2 files changed, 42 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index 278867a31950..eae73b58248b 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -35,11 +35,15 @@ #define SPI_CMD_REG 0x0018 #define SPI_STATUS0_REG 0x001c #define SPI_PAD_SEL_REG 0x0024 +#define SPI_CFG2_REG 0x0028 #define SPI_CFG0_SCK_HIGH_OFFSET 0 #define SPI_CFG0_SCK_LOW_OFFSET 8 #define SPI_CFG0_CS_HOLD_OFFSET 16 #define SPI_CFG0_CS_SETUP_OFFSET 24 +#define SPI_ADJUST_CFG0_SCK_LOW_OFFSET 16 +#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0 +#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16 #define SPI_CFG1_CS_IDLE_OFFSET 0 #define SPI_CFG1_PACKET_LOOP_OFFSET 8 @@ -55,6 +59,8 @@ #define SPI_CMD_RST BIT(2) #define SPI_CMD_PAUSE_EN BIT(4) #define SPI_CMD_DEASSERT BIT(5) +#define SPI_CMD_SAMPLE_SEL BIT(6) +#define SPI_CMD_CS_POL BIT(7) #define SPI_CMD_CPHA BIT(8) #define SPI_CMD_CPOL BIT(9) #define SPI_CMD_RX_DMA BIT(10) @@ -80,6 +86,8 @@ struct mtk_spi_compatible { bool need_pad_sel; /* Must explicitly send dummy Tx bytes to do Rx only transfer */ bool must_tx; + /* some IC design adjust cfg register to enhance time accuracy */ + bool enhance_timing; }; struct mtk_spi { @@ -108,6 +116,8 @@ static const struct mtk_spi_compatible mt8173_compat = { static const struct mtk_chip_config mtk_default_chip_info = { .rx_mlsb = 1, .tx_mlsb = 1, + .cs_pol = 0, + .sample_sel = 0, }; static const struct of_device_id mtk_spi_of_match[] = { @@ -182,6 +192,17 @@ static int mtk_spi_prepare_message(struct spi_master *master, reg_val |= SPI_CMD_RX_ENDIAN; #endif + if (mdata->dev_comp->enhance_timing) { + if (chip_config->cs_pol) + reg_val |= SPI_CMD_CS_POL; + else + reg_val &= ~SPI_CMD_CS_POL; + if (chip_config->sample_sel) + reg_val |= SPI_CMD_SAMPLE_SEL; + else + reg_val &= ~SPI_CMD_SAMPLE_SEL; + } + /* set finish and pause interrupt always enable */ reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE; @@ -233,11 +254,25 @@ static void mtk_spi_prepare_transfer(struct spi_master *master, sck_time = (div + 1) / 2; cs_time = sck_time * 2; - reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET); - reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); - reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); - reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET); - writel(reg_val, mdata->base + SPI_CFG0_REG); + if (mdata->dev_comp->enhance_timing) { + reg_val |= (((sck_time - 1) & 0xffff) + << SPI_CFG0_SCK_HIGH_OFFSET); + reg_val |= (((sck_time - 1) & 0xffff) + << SPI_ADJUST_CFG0_SCK_LOW_OFFSET); + writel(reg_val, mdata->base + SPI_CFG2_REG); + reg_val |= (((cs_time - 1) & 0xffff) + << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); + reg_val |= (((cs_time - 1) & 0xffff) + << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); + writel(reg_val, mdata->base + SPI_CFG0_REG); + } else { + reg_val |= (((sck_time - 1) & 0xff) + << SPI_CFG0_SCK_HIGH_OFFSET); + reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); + reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); + reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET); + writel(reg_val, mdata->base + SPI_CFG0_REG); + } reg_val = readl(mdata->base + SPI_CFG1_REG); reg_val &= ~SPI_CFG1_CS_IDLE_MASK; diff --git a/include/linux/platform_data/spi-mt65xx.h b/include/linux/platform_data/spi-mt65xx.h index 54b04483976c..ba4e4bb70262 100644 --- a/include/linux/platform_data/spi-mt65xx.h +++ b/include/linux/platform_data/spi-mt65xx.h @@ -16,5 +16,7 @@ struct mtk_chip_config { u32 tx_mlsb; u32 rx_mlsb; + u32 cs_pol; + u32 sample_sel; }; #endif -- 2.11.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] spi: mediatek: add spi support for mt7622 IC 2017-06-10 4:46 [PATCH v2 0/2] add mt7622 spi support Leilk Liu [not found] ` <1497069989-30584-1-git-send-email-leilk.liu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> @ 2017-06-10 4:46 ` Leilk Liu [not found] ` <1497069989-30584-3-git-send-email-leilk.liu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> 1 sibling, 1 reply; 5+ messages in thread From: Leilk Liu @ 2017-06-10 4:46 UTC (permalink / raw) To: Mark Brown Cc: Mark Rutland, Matthias Brugger, Sascha Hauer, devicetree, linux-kernel, linux-arm-kernel, linux-spi, linux-mediatek, sean.wang, Leilk Liu this patch add support for mt7622 IC. Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> --- drivers/spi/spi-mt65xx.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index eae73b5..4bf6495 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -104,6 +104,12 @@ struct mtk_spi { }; static const struct mtk_spi_compatible mtk_common_compat; + +static const struct mtk_spi_compatible mt7622_compat = { + .must_tx = true, + .adjust_reg = true, +}; + static const struct mtk_spi_compatible mt8173_compat = { .need_pad_sel = true, .must_tx = true, @@ -127,6 +133,9 @@ struct mtk_spi { { .compatible = "mediatek,mt6589-spi", .data = (void *)&mtk_common_compat, }, + { .compatible = "mediatek,mt7622-spi", + .data = (void *)&mt7622_compat, + }, { .compatible = "mediatek,mt8135-spi", .data = (void *)&mtk_common_compat, }, -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 5+ messages in thread
[parent not found: <1497069989-30584-3-git-send-email-leilk.liu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>]
* Re: [PATCH v2 2/2] spi: mediatek: add spi support for mt7622 IC [not found] ` <1497069989-30584-3-git-send-email-leilk.liu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> @ 2017-06-11 12:22 ` kbuild test robot 0 siblings, 0 replies; 5+ messages in thread From: kbuild test robot @ 2017-06-11 12:22 UTC (permalink / raw) To: Leilk Liu Cc: kbuild-all-JC7UmRfGjtg, Mark Brown, Mark Rutland, Matthias Brugger, Sascha Hauer, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-spi-u79uwXL29TY76Z2rM5mHXA, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, sean.wang-NuS5LvNUpcJWk0Htik3J/w, Leilk Liu [-- Attachment #1: Type: text/plain, Size: 1377 bytes --] Hi Leilk, [auto build test ERROR on spi/for-next] [also build test ERROR on v4.12-rc4 next-20170609] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Leilk-Liu/add-mt7622-spi-support/20170611-185202 base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next config: xtensa-allmodconfig (attached as .config) compiler: xtensa-linux-gcc (GCC) 4.9.0 reproduce: wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree make.cross ARCH=xtensa All errors (new ones prefixed by >>): >> drivers//spi/spi-mt65xx.c:110:2: error: unknown field 'adjust_reg' specified in initializer .adjust_reg = true, ^ vim +/adjust_reg +110 drivers//spi/spi-mt65xx.c 104 }; 105 106 static const struct mtk_spi_compatible mtk_common_compat; 107 108 static const struct mtk_spi_compatible mt7622_compat = { 109 .must_tx = true, > 110 .adjust_reg = true, 111 }; 112 113 static const struct mtk_spi_compatible mt8173_compat = { --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation [-- Attachment #2: .config.gz --] [-- Type: application/gzip, Size: 50160 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-06-13 21:09 UTC | newest]
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2017-06-10 4:46 [PATCH v2 0/2] add mt7622 spi support Leilk Liu
[not found] ` <1497069989-30584-1-git-send-email-leilk.liu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2017-06-10 4:46 ` [PATCH v2 1/2] spi: mediatek: adjust register to enhance time accuracy Leilk Liu
2017-06-13 21:09 ` Applied "spi: mediatek: adjust register to enhance time accuracy" to the spi tree Mark Brown
2017-06-10 4:46 ` [PATCH v2 2/2] spi: mediatek: add spi support for mt7622 IC Leilk Liu
[not found] ` <1497069989-30584-3-git-send-email-leilk.liu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2017-06-11 12:22 ` kbuild test robot
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