From: Alain Volmat <alain.volmat@st.com>
To: <broonie@kernel.org>, <amelie.delaunay@st.com>
Cc: <mcoquelin.stm32@gmail.com>, <alexandre.torgue@st.com>,
<linux-spi@vger.kernel.org>,
<linux-stm32@st-md-mailman.stormreply.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <fabrice.gasnier@st.com>,
<alain.volmat@st.com>
Subject: [PATCH 11/18] spi: stm32: fix fifo threshold level in case of short transfer
Date: Wed, 5 Aug 2020 09:02:06 +0200 [thread overview]
Message-ID: <1596610933-32599-12-git-send-email-alain.volmat@st.com> (raw)
In-Reply-To: <1596610933-32599-1-git-send-email-alain.volmat@st.com>
From: Amelie Delaunay <amelie.delaunay@st.com>
When transfer is shorter than half of the fifo, set the data packet size
up to transfer size instead of up to half of the fifo.
Check also that threshold is set at least to 1 data frame.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alain Volmat <alain.volmat@st.com>
---
drivers/spi/spi-stm32.c | 23 +++++++++++++++--------
1 file changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 7e3894455331..0eda9903e11e 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -459,20 +459,24 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
/**
* stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
* @spi: pointer to the spi controller data structure
+ * @xfer_len: length of the message to be transferred
*/
-static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi)
+static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
{
- u32 fthlv, half_fifo;
+ u32 fthlv, half_fifo, packet;
/* data packet should not exceed 1/2 of fifo space */
half_fifo = (spi->fifo_size / 2);
+ /* data_packet should not exceed transfer length */
+ packet = (half_fifo > xfer_len) ? xfer_len : half_fifo;
+
if (spi->cur_bpw <= 8)
- fthlv = half_fifo;
+ fthlv = packet;
else if (spi->cur_bpw <= 16)
- fthlv = half_fifo / 2;
+ fthlv = packet / 2;
else
- fthlv = half_fifo / 4;
+ fthlv = packet / 4;
/* align packet size with data registers access */
if (spi->cur_bpw > 8)
@@ -480,6 +484,9 @@ static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi)
else
fthlv -= (fthlv % 4); /* multiple of 4 */
+ if (!fthlv)
+ fthlv = 1;
+
return fthlv;
}
@@ -1385,7 +1392,7 @@ static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_DSIZE, bpw);
- spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi);
+ spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
fthlv = spi->cur_fthlv - 1;
cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
@@ -1571,6 +1578,8 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
spin_lock_irqsave(&spi->lock, flags);
+ spi->cur_xferlen = transfer->len;
+
if (spi->cur_bpw != transfer->bits_per_word) {
spi->cur_bpw = transfer->bits_per_word;
spi->cfg->set_bpw(spi);
@@ -1618,8 +1627,6 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
goto out;
}
- spi->cur_xferlen = transfer->len;
-
dev_dbg(spi->dev, "transfer communication mode set to %d\n",
spi->cur_comm);
dev_dbg(spi->dev,
--
2.7.4
next prev parent reply other threads:[~2020-08-05 7:23 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-05 7:01 [PATCH 00/18] spi: stm32: various driver enhancements Alain Volmat
2020-08-05 7:01 ` [PATCH 01/18] spi: stm32-spi: driver uses reset controller only at init Alain Volmat
2020-08-05 7:01 ` [PATCH 02/18] spi: stm32-spi: defer probe for reset Alain Volmat
2020-08-05 10:49 ` Mark Brown
2020-08-07 13:42 ` Alain Volmat
2020-08-07 14:01 ` Mark Brown
2020-08-05 7:01 ` [PATCH 03/18] spi: stm32h7: remove unused mode fault MODF event handling Alain Volmat
2020-08-05 10:51 ` Mark Brown
2020-08-05 7:01 ` [PATCH 04/18] spi: stm32: use bitfield macros Alain Volmat
2020-08-05 7:02 ` [PATCH 05/18] spi: stm32h7: replace private SPI_1HZ_NS with NSEC_PER_SEC Alain Volmat
2020-08-05 7:02 ` [PATCH 06/18] spi: stm32h7: fix irq handler Alain Volmat
2020-08-05 7:02 ` [PATCH 07/18] spi: stm32h7: rework rx fifo read function Alain Volmat
2020-08-05 7:02 ` [PATCH 08/18] spi: stm32h7: fix dbg/warn/err conditions in irq handler Alain Volmat
2020-08-05 7:02 ` [PATCH 09/18] spi: stm32h7: fix race condition at end of transfer Alain Volmat
2020-08-05 10:53 ` Mark Brown
2020-08-05 7:02 ` [PATCH 10/18] spi: stm32: wait for completion in transfer_one() Alain Volmat
2020-08-05 10:58 ` Mark Brown
2020-08-05 7:02 ` Alain Volmat [this message]
2020-08-05 10:59 ` [PATCH 11/18] spi: stm32: fix fifo threshold level in case of short transfer Mark Brown
2020-08-05 7:02 ` [PATCH 12/18] spi: stm32: move spi disable out of irq handler Alain Volmat
2020-08-05 11:01 ` Mark Brown
2020-08-05 7:02 ` [PATCH 13/18] spi: stm32h7: fix handling of dma transfer completed Alain Volmat
2020-08-05 11:02 ` Mark Brown
2020-08-05 7:02 ` [PATCH 14/18] spi: stm32: improve suspend/resume management Alain Volmat
2020-08-05 7:02 ` [PATCH 15/18] spi: stm32: fix stm32_spi_prepare_mbr in case of odd clk_rate Alain Volmat
2020-08-05 11:02 ` Mark Brown
2020-08-05 7:02 ` [PATCH 16/18] spi: stm32: always perform registers configuration prior to transfer Alain Volmat
2020-08-05 11:03 ` Mark Brown
2020-08-05 7:02 ` [PATCH 17/18] spi: stm32: properly handle 0 byte transfer Alain Volmat
2020-08-05 7:02 ` [PATCH 18/18] spi: stm32h7: ensure message are smaller than max size Alain Volmat
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