From: Tudor Ambarus <tudor.ambarus@linaro.org>
To: Michael Walle <michael@walle.cc>
Cc: Serge Semin <fancer.lancer@gmail.com>,
Sergiu.Moga@microchip.com, Mark Brown <broonie@kernel.org>,
Tudor Ambarus <tudor.ambarus@microchip.com>,
Pratyush Yadav <pratyush@kernel.org>,
miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
Nicolas.Ferre@microchip.com, alexandre.belloni@bootlin.com,
Claudiu.Beznea@microchip.com, chin-ting_kuo@aspeedtech.com,
clg@kaod.org, joel@jms.id.au, andrew@aj.id.au,
kdasu.kdev@gmail.com, han.xu@nxp.com, john.garry@huawei.com,
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Subject: Re: [PATCH] spi: Replace `dummy.nbytes` with `dummy.ncycles`
Date: Thu, 9 Mar 2023 12:42:35 +0200 [thread overview]
Message-ID: <1849e2c8-54f5-9e56-4ed8-8b0e4a826d04@linaro.org> (raw)
In-Reply-To: <f647e713a65f5d3f0f2e3af95c4d0a89@walle.cc>
On 09.03.2023 10:38, Michael Walle wrote:
>> In an ideal world, where both the controller and the device talk about
>> dummy number of cycles, I would agree with you, buswidth and dtr should
>> not be relevant for the number of dummy cycles. But it seems that there
>> are old controllers (e.g. spi-hisi-sfc-v3xx.c, spi-mt65xx.c, spi-mxic.c)
>> that support buswidths > 1 and work only with dummy nbytes, they are not
>> capable of specifying a smaller granularity (ncycles). Thus the older
>> controllers would have to convert the dummy ncycles to dummy nbytes.
>> Since mixed transfer modes are a thing (see jesd251, it talks about
>> 4S-4D-4D), where single transfer mode (S) can be mixed with double
>> transfer mode (D) for a command, the controller would have to guess the
>> buswidth and dtr of the dummy. Shall they replicate the buswidth and dtr
>> of the address or of the data? There's no rule for that.
>
> But in the end that doesn't matter because they are just dummy clock
> cycles and the mode will only affect the data/address/command. Therefore,
> the controller is free to choose the mode that suits it best.
> > But that begs the question, is ncycles in regard to DTR or SDR? That is,
> are you counting just one type of edges or both the falling and rising
> edges. The smallest granularity would be ncycles in regard of DTR. To me,
> it's not obvious what the SEMPER Nano Flash [1] uses. I'd say we choose
> the smallest granularty in spi-mem to be future proof and maybe provide
> some spi-mem helper to help setting the cycles for SDR/DTR. As an example,
> if you want to wait 4 cycles in SDR you'd have ncycles=8 in spi-mem.
>
No, we can't invent our own measuring units. We have cycles and half
cycles (regardless of the transfer mode used (STR, DTR)).
> So you won't need the mode nor the dtr property.
>
> -michael
>
> [1]
> https://www.infineon.com/dgdl/Infineon-S25FS256T_256Mb_SEMPER_Nano_Flash_Quad_SPI_1.8V-DataSheet-v01_00-EN.pdf?fileId=8ac78c8c80027ecd0180740c5a46707a
next prev parent reply other threads:[~2023-03-09 10:44 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-11 17:45 [PATCH] spi: Replace `dummy.nbytes` with `dummy.ncycles` Sergiu Moga
2022-09-12 9:44 ` Patrice CHOTARD
2022-09-12 10:58 ` Tudor.Ambarus
2022-09-12 11:52 ` Mark Brown
2022-09-25 22:03 ` Serge Semin
2022-09-26 9:05 ` Sergiu.Moga
2022-09-26 17:24 ` Serge Semin
2022-09-27 8:21 ` Sergiu.Moga
2023-03-08 9:04 ` Tudor Ambarus
2023-03-09 8:38 ` Michael Walle
2023-03-09 10:42 ` Tudor Ambarus [this message]
2023-03-09 10:56 ` Michael Walle
2023-03-09 12:09 ` Tudor Ambarus
2023-03-09 12:35 ` Michael Walle
2023-03-09 13:23 ` Tudor Ambarus
2023-03-09 13:33 ` Michael Walle
2023-03-09 13:54 ` Tudor Ambarus
2023-03-09 14:01 ` Michael Walle
2023-03-09 14:19 ` Chuanhong Guo
2023-03-09 15:41 ` Michael Walle
2023-03-09 15:41 ` Tudor Ambarus
2023-03-04 5:59 ` Tudor Ambarus
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