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Date: Mon, 18 Dec 2023 23:10:20 +0100 (CET)
From: Richard Weinberger <richard@nod.at>
To: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
Cc: Mark Brown <broonie@kernel.org>, Tudor Ambarus <tudor.ambarus@linaro.org>, 
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References: <20231125092137.2948-1-amit.kumar-mahapatra@amd.com>
Subject: Re: [PATCH v11 00/10] spi: Add support for stacked/parallel
 memories
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----- Urspr=C3=BCngliche Mail -----
> Von: "Amit Kumar Mahapatra" <amit.kumar-mahapatra@amd.com>

> This patch series updated the spi-nor, spi core and the AMD-Xilinx GQSPI
> driver to add stacked and parallel memories support.

I wish the series had a real cover letter which explains the big picture
in more detail.

What I didn't really get so far, is it really necessary to support multiple
chip selects within a single mtd?
You changes introduce hard to maintain changes into the spi-nor/mtd core co=
de
which alert me.
Why can't we have one mtd for each cs and, if needed, combine them later?
We have drivers such as mtdconcat for reasons.

Thanks,
//richard