Re: [PATCH 3/3] spi: dw_spi: refine the IRQ mode working flow

[Feng Tang <feng.tang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>]

On Wed, 20 Jan 2010 20:44:03 +0800
Jean-Hugues Deschenes <jean-hugues.deschenes-YGVykHU+fedBDgjK7y7TUQ@public.gmane.org> wrote:

>
> >>     
> >
> > For FIFO depth, it depends on each specific implementation based on
> > DW core, and interface driver would better set it. If fifo_len is
> > not set in IRQ mode, core driver will set 0 as the TX interrupt
> > threshold, which will only trigger the TXE IRQ when the TX FIFO is
> > fully empty. This is my design thought. 
> I'm sorry; At first, I was under the impression that it referred to a 
> software FIFO.
> ...So could this be auto-detected from the [RT]XFTLR registers, then?
> 

Yep, really a good idea, from the HW spec, the depth could be detected
from [RT}XTLR, will submit a patch for this.

Thanks,
Feng

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