Re: [PATCH 2/6 Revised] SPI omap2_mcspi: Add max_clk_div field to mcspi platform config

[Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>]

* Scott Ellis <scott-oZqG5KApg2M/jFmSBShxMA@public.gmane.org> [100315 13:27]:
> > Hmm now it looks like you're missing 3630 handling?
> > 
> > If the max_clk_div is 0x0f for 2420 and 2430, then you
> > can just check for cpu_is_omap24xx(). If it's only
> > different for 2420, then you can check for cpu_is_omap2420().
> > 
> > That way it should be more future proof, and you don't
> > need to change it for new processors.
> > 
> Anand Gadiyar <gadiyar <at> ti.com> verified 0x0f for the 2430.
> 
> I think SWPU177D is the correct TRM for the omap3630 and if so then 0x0c
> is the correct value.
> 
> I did not verify the omap44xx value and just assumed similar to the
> omap3's. My bad.
> 
> Can you or someone point me to links for the omap2420 and the omap44xx
> TRMs? I'm not having any luck finding them.

I don't think those are publicly available yet for 4430 and still for
2420..

But looks like 2420, 2430 and 4430 TRMs says that 0xf = 32768
max divider for CLKD.

Only 3430 and 3630 TRMs says 0xd, 0xe, 0xf = Division not supported.

But then again, the TRMs can have errors.

> Then it can be verified whether a cpu_is_omap24xx() check is sufficient.
> It probably is.

Then the 4430 TRM must have an error.. Can somebody from TI
confirm the CLKD max value for 4430 please?
 
> Or if someone with access to those manuals could do a quick check...
> 
> It's the max value of the MCSPI_CHxCONF.CLKD register field.

Regards,

Tony

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