Assert CS, wait for IRQ, write data sequence

[Sergii Kovalchuk <sentinelofsetch-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]

Hi,

I'm implementing an SPI protocol driver for TI WL12xx combo chip. According to 
the spec, for write transaction I should complete the following sequence:

1. Assert CS
2. Wait until chip will trigger IRQ
3. Write data

Looking at spi_transfer structure I wondering, how I can implement such logic 
- there is no explicit ways to implement "wait for an event" within single 
spi_message processing.
 
As current workarround I use a simple delay in 5 us, but for sleep states it 
might be not sufficient, since wake-up time are ususally greater.


It would be appropriate to assert CS manually, wait for IRQ and then start the 
data transfer, but may be there is some more essential way to accomplish this?

--
Best regards,
Sergii Kovalchuk

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