* [PATCH 1/2] spi/fsl-espi: make the clock computation easier to read
@ 2012-03-15 17:42 Sebastian Andrzej Siewior
[not found] ` <1331833352-15058-1-git-send-email-bigeasy-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
0 siblings, 1 reply; 4+ messages in thread
From: Sebastian Andrzej Siewior @ 2012-03-15 17:42 UTC (permalink / raw)
To: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Cc: Mingkai Hu, Sebastian Andrzej Siewior
The -1 +1 thingy should probably do what DIV_ROUND_UP does. The 4 is 2
the "platform_clock => sysclock" and 2 from the computation part. The 64
is the same 4 times 16.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
---
drivers/spi/spi-fsl-espi.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c
index d770f03..43350f9 100644
--- a/drivers/spi/spi-fsl-espi.c
+++ b/drivers/spi/spi-fsl-espi.c
@@ -180,7 +180,7 @@ static int fsl_espi_setup_transfer(struct spi_device *spi,
if ((mpc8xxx_spi->spibrg / hz) > 64) {
cs->hw_mode |= CSMODE_DIV16;
- pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
+ pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
"Will use %d Hz instead.\n", dev_name(&spi->dev),
@@ -188,7 +188,7 @@ static int fsl_espi_setup_transfer(struct spi_device *spi,
if (pm > 16)
pm = 16;
} else {
- pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
+ pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
}
if (pm)
pm--;
--
1.7.9.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] spi/fsl-espi: Make sure pm is within 2..32
[not found] ` <1331833352-15058-1-git-send-email-bigeasy-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
@ 2012-03-15 17:42 ` Sebastian Andrzej Siewior
[not found] ` <1331833352-15058-2-git-send-email-bigeasy-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
2012-03-15 21:15 ` [PATCH 1/2] spi/fsl-espi: make the clock computation easier to read Grant Likely
1 sibling, 1 reply; 4+ messages in thread
From: Sebastian Andrzej Siewior @ 2012-03-15 17:42 UTC (permalink / raw)
To: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Cc: Mingkai Hu, Sebastian Andrzej Siewior
The reference manual says that pm has to stay within 2 and 32. So the
lowest frequency is 32 and DIV16 set, the highest is 2 and DIV16 unset.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
---
drivers/spi/spi-fsl-espi.c | 10 ++++++----
1 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c
index 43350f9..7523a24 100644
--- a/drivers/spi/spi-fsl-espi.c
+++ b/drivers/spi/spi-fsl-espi.c
@@ -182,16 +182,18 @@ static int fsl_espi_setup_transfer(struct spi_device *spi,
cs->hw_mode |= CSMODE_DIV16;
pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
- WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
+ WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
"Will use %d Hz instead.\n", dev_name(&spi->dev),
- hz, mpc8xxx_spi->spibrg / 1024);
- if (pm > 16)
- pm = 16;
+ hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
+ if (pm > 33)
+ pm = 33;
} else {
pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
}
if (pm)
pm--;
+ if (pm < 2)
+ pm = 2;
cs->hw_mode |= CSMODE_PM(pm);
--
1.7.9.1
------------------------------------------------------------------------------
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] spi/fsl-espi: make the clock computation easier to read
[not found] ` <1331833352-15058-1-git-send-email-bigeasy-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
2012-03-15 17:42 ` [PATCH 2/2] spi/fsl-espi: Make sure pm is within 2..32 Sebastian Andrzej Siewior
@ 2012-03-15 21:15 ` Grant Likely
1 sibling, 0 replies; 4+ messages in thread
From: Grant Likely @ 2012-03-15 21:15 UTC (permalink / raw)
To: Sebastian Andrzej Siewior,
spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Cc: Mingkai Hu, Sebastian Andrzej Siewior
On Thu, 15 Mar 2012 18:42:31 +0100, Sebastian Andrzej Siewior <bigeasy-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org> wrote:
> The -1 +1 thingy should probably do what DIV_ROUND_UP does. The 4 is 2
> the "platform_clock => sysclock" and 2 from the computation part. The 64
> is the same 4 times 16.
>
> Signed-off-by: Sebastian Andrzej Siewior <bigeasy-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
Applied, thanks.
g.
> ---
> drivers/spi/spi-fsl-espi.c | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c
> index d770f03..43350f9 100644
> --- a/drivers/spi/spi-fsl-espi.c
> +++ b/drivers/spi/spi-fsl-espi.c
> @@ -180,7 +180,7 @@ static int fsl_espi_setup_transfer(struct spi_device *spi,
>
> if ((mpc8xxx_spi->spibrg / hz) > 64) {
> cs->hw_mode |= CSMODE_DIV16;
> - pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
> + pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
>
> WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
> "Will use %d Hz instead.\n", dev_name(&spi->dev),
> @@ -188,7 +188,7 @@ static int fsl_espi_setup_transfer(struct spi_device *spi,
> if (pm > 16)
> pm = 16;
> } else {
> - pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
> + pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
> }
> if (pm)
> pm--;
> --
> 1.7.9.1
>
--
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.
------------------------------------------------------------------------------
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] spi/fsl-espi: Make sure pm is within 2..32
[not found] ` <1331833352-15058-2-git-send-email-bigeasy-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
@ 2012-03-15 21:15 ` Grant Likely
0 siblings, 0 replies; 4+ messages in thread
From: Grant Likely @ 2012-03-15 21:15 UTC (permalink / raw)
To: Sebastian Andrzej Siewior,
spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Cc: Mingkai Hu, Sebastian Andrzej Siewior
On Thu, 15 Mar 2012 18:42:32 +0100, Sebastian Andrzej Siewior <bigeasy-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org> wrote:
> The reference manual says that pm has to stay within 2 and 32. So the
> lowest frequency is 32 and DIV16 set, the highest is 2 and DIV16 unset.
>
> Signed-off-by: Sebastian Andrzej Siewior <bigeasy-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
Applied, thanks.
g.
> ---
> drivers/spi/spi-fsl-espi.c | 10 ++++++----
> 1 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c
> index 43350f9..7523a24 100644
> --- a/drivers/spi/spi-fsl-espi.c
> +++ b/drivers/spi/spi-fsl-espi.c
> @@ -182,16 +182,18 @@ static int fsl_espi_setup_transfer(struct spi_device *spi,
> cs->hw_mode |= CSMODE_DIV16;
> pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
>
> - WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
> + WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
> "Will use %d Hz instead.\n", dev_name(&spi->dev),
> - hz, mpc8xxx_spi->spibrg / 1024);
> - if (pm > 16)
> - pm = 16;
> + hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
> + if (pm > 33)
> + pm = 33;
> } else {
> pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
> }
> if (pm)
> pm--;
> + if (pm < 2)
> + pm = 2;
>
> cs->hw_mode |= CSMODE_PM(pm);
>
> --
> 1.7.9.1
>
--
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.
------------------------------------------------------------------------------
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2012-03-15 17:42 [PATCH 1/2] spi/fsl-espi: make the clock computation easier to read Sebastian Andrzej Siewior
[not found] ` <1331833352-15058-1-git-send-email-bigeasy-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
2012-03-15 17:42 ` [PATCH 2/2] spi/fsl-espi: Make sure pm is within 2..32 Sebastian Andrzej Siewior
[not found] ` <1331833352-15058-2-git-send-email-bigeasy-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
2012-03-15 21:15 ` Grant Likely
2012-03-15 21:15 ` [PATCH 1/2] spi/fsl-espi: make the clock computation easier to read Grant Likely
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