* [PATCH] spi: Change FIFO flush operation and spi channel off
@ 2012-05-23 12:29 Kyoungil Kim
[not found] ` <009f01cd38df$c00cf6f0$4026e4d0$%kim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
0 siblings, 1 reply; 2+ messages in thread
From: Kyoungil Kim @ 2012-05-23 12:29 UTC (permalink / raw)
To: spi-devel-general, linux-samsung-soc
Cc: 'Grant Likely', 'Kukjin Kim',
'Kyoungil Kim'
Setting SW_RST does TX/RX FIFO flush.
After FIFO flush, SW_RST should be cleared.
The above setting and clearing SW_RST operation should be done after spi channel off.
Signed-off-by: Kyoungil Kim <ki0351.kim@samsung.com>
---
drivers/spi/spi-s3c64xx.c | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 972a94c..293f097 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -191,6 +191,10 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
writel(0, regs + S3C64XX_SPI_PACKET_CNT);
val = readl(regs + S3C64XX_SPI_CH_CFG);
+ val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
+ writel(val, regs + S3C64XX_SPI_CH_CFG);
+
+ val = readl(regs + S3C64XX_SPI_CH_CFG);
val |= S3C64XX_SPI_CH_SW_RST;
val &= ~S3C64XX_SPI_CH_HS_EN;
writel(val, regs + S3C64XX_SPI_CH_CFG);
@@ -224,10 +228,6 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
val = readl(regs + S3C64XX_SPI_MODE_CFG);
val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
writel(val, regs + S3C64XX_SPI_MODE_CFG);
-
- val = readl(regs + S3C64XX_SPI_CH_CFG);
- val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
- writel(val, regs + S3C64XX_SPI_CH_CFG);
}
static void s3c64xx_spi_dmacb(void *data)
--
1.7.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] spi: Change FIFO flush operation and spi channel off
[not found] ` <009f01cd38df$c00cf6f0$4026e4d0$%kim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
@ 2012-05-25 22:57 ` Grant Likely
0 siblings, 0 replies; 2+ messages in thread
From: Grant Likely @ 2012-05-25 22:57 UTC (permalink / raw)
To: Kyoungil Kim, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA
Cc: 'Kukjin Kim', 'Kyoungil Kim'
On Wed, 23 May 2012 21:29:51 +0900, Kyoungil Kim <ki0351.kim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
> Setting SW_RST does TX/RX FIFO flush.
> After FIFO flush, SW_RST should be cleared.
> The above setting and clearing SW_RST operation should be done after spi channel off.
>
> Signed-off-by: Kyoungil Kim <ki0351.kim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Applied, thanks.
g.
> ---
> drivers/spi/spi-s3c64xx.c | 8 ++++----
> 1 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index 972a94c..293f097 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -191,6 +191,10 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
> writel(0, regs + S3C64XX_SPI_PACKET_CNT);
>
> val = readl(regs + S3C64XX_SPI_CH_CFG);
> + val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
> + writel(val, regs + S3C64XX_SPI_CH_CFG);
> +
> + val = readl(regs + S3C64XX_SPI_CH_CFG);
> val |= S3C64XX_SPI_CH_SW_RST;
> val &= ~S3C64XX_SPI_CH_HS_EN;
> writel(val, regs + S3C64XX_SPI_CH_CFG);
> @@ -224,10 +228,6 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
> val = readl(regs + S3C64XX_SPI_MODE_CFG);
> val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
> writel(val, regs + S3C64XX_SPI_MODE_CFG);
> -
> - val = readl(regs + S3C64XX_SPI_CH_CFG);
> - val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
> - writel(val, regs + S3C64XX_SPI_CH_CFG);
> }
>
> static void s3c64xx_spi_dmacb(void *data)
> --
> 1.7.1
>
>
--
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies, Ltd.
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2012-05-23 12:29 [PATCH] spi: Change FIFO flush operation and spi channel off Kyoungil Kim
[not found] ` <009f01cd38df$c00cf6f0$4026e4d0$%kim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2012-05-25 22:57 ` Grant Likely
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