From: Mark Brown <broonie@opensource.wolfsonmicro.com>
To: Manish Badarkhe <badarkhe.manish@gmail.com>
Cc: Laxman Dewangan <ldewangan@nvidia.com>,
grant.likely@secretlab.ca, rob.herring@calxeda.com,
linux-doc@vger.kernel.org, devicetree-discuss@lists.ozlabs.org,
linux-kernel@vger.kernel.org,
spi-devel-general@lists.sourceforge.net,
linux-tegra@vger.kernel.org, swarren@nvidia.com
Subject: Re: [PATCH V3] spi: tegra114: add spi driver
Date: Fri, 22 Feb 2013 18:02:26 +0000 [thread overview]
Message-ID: <20130222180226.GC19796@opensource.wolfsonmicro.com> (raw)
In-Reply-To: <CAKDJKT5yngpZQC-ZvHSaKeBVHW97wo4QwLSXQ4KsVWCs5J1YKg@mail.gmail.com>
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On Fri, Feb 22, 2013 at 07:59:11PM +0530, Manish Badarkhe wrote:
> On Fri, Feb 22, 2013 at 6:07 PM, Laxman Dewangan <ldewangan@nvidia.com> wrote:
> > Add SPI driver for NVIDIA's Tegra114 SPI controller. This controller
> > is different than the older SoCs SPI controller in internal design as
> > well as register interface.
> >
> > This driver supports the:
> > - non DMA based transfer for smaller transfer i.e. less than FIFO depth.
> > - APB DMA based transfer for lager transfer i.e. more than FIFO depth.
>
> s/lager/larger
>
> > - Clock gating through runtime PM callbacks.
> > - registration through DT only.
Delete unneeded context from your replies, we shouldn't need to page
through the entire patch because you've noticed a spelling error...
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next prev parent reply other threads:[~2013-02-22 18:02 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-22 12:37 [PATCH V3] spi: tegra114: add spi driver Laxman Dewangan
[not found] ` <1361536659-23225-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-02-22 14:29 ` Manish Badarkhe
2013-02-22 18:02 ` Mark Brown [this message]
2013-03-03 12:49 ` Manish Badarkhe
[not found] ` <CAKDJKT5yngpZQC-ZvHSaKeBVHW97wo4QwLSXQ4KsVWCs5J1YKg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-03-02 23:09 ` Grant Likely
2013-03-28 11:38 ` Laxman Dewangan
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