From: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>
To: Trent Piepho <tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Fabio Estevam
<fabio.estevam-KZfg59tc24xl57MIdRCFDg@public.gmane.org>,
spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org,
Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [PATCH V2 03/12] spi/mxs: Change flag arguments in txrx functions to bit flags
Date: Wed, 3 Apr 2013 01:24:30 +0200 [thread overview]
Message-ID: <201304030124.30625.marex@denx.de> (raw)
In-Reply-To: <1364905195-24286-3-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Dear Trent Piepho,
> There are three flag arguments to the PIO and DMA txrx functions. Two
> are passed as pointers to integers, even though they are input only
> and not modified, which makes no sense to do. The third is passed as
> an integer.
>
> The compiler must use an argument register or stack variable for each
> flag this way. By using bitflags in a single flag argument more
> efficient and smaller code is produced since all the flags can fit in
> a single register. And all the flag arguments get cumbersome,
> especially when more are added for things like GPIO chipselects.
>
> The "first" flag is never used, so can just be deleted.
>
> The "last" flag is renamed to DEASSERT_CS, since that's really what it
> does. The spi_transfer cs_change flag means that CS might be
> de-asserted on a transfer which is not last and not de-assert on the
> last transfer, so it is not which transfer is the last we need to know
> but rather the transfers which after which CS should be de-asserted.
>
> This also extends the driver to not ignore cs_change when setting the
> DEASSERT_CS nee "last" flag.
>
> Signed-off-by: Trent Piepho <tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>
> Cc: Fabio Estevam <fabio.estevam-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> Cc: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> drivers/spi/spi-mxs.c | 55
> ++++++++++++++++++++++++++++--------------------- 1 file changed, 31
> insertions(+), 24 deletions(-)
>
> diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
> index 7eb4bc9..3064304 100644
> --- a/drivers/spi/spi-mxs.c
> +++ b/drivers/spi/spi-mxs.c
> @@ -58,6 +58,13 @@
>
> #define SG_MAXLEN 0xff00
>
> +/*
> + * Flags for txrx functions. More efficient that using an argument
> register for + * each one.
> + */
> +#define TXRX_WRITE 1 /* This is a write */
> +#define TXRX_DEASSERT_CS 2 /* De-assert CS at end of txrx */
> +
Use (1 << n) here as these are bitfield flags.
[...]
> @@ -409,10 +418,9 @@ static int mxs_spi_transfer_one(struct spi_master
> *master, if (status)
> break;
>
> - if (&t->transfer_list == m->transfers.next)
> - first = 1;
> - if (&t->transfer_list == m->transfers.prev)
> - last = 1;
> + /* De-assert on last transfer, inverted by cs_change flag */
> + flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
> + TXRX_DEASSERT_CS : 0;
Make this into an if-else block, this really is hard to parse at first glance.
> if ((t->rx_buf && t->tx_buf) || (t->rx_dma && t->tx_dma)) {
> dev_err(ssp->dev,
> "Cannot send and receive simultaneously\n");
[...]
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next prev parent reply other threads:[~2013-04-02 23:24 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-02 12:19 [PATCH V2 01/12] spi/mxs: Always set LOCK_CS Trent Piepho
[not found] ` <1364905195-24286-1-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-04-02 12:19 ` [PATCH V2 02/12] spi/mxs: Remove mxs_spi_enable and mxs_spi_disable Trent Piepho
2013-04-02 12:19 ` [PATCH V2 03/12] spi/mxs: Change flag arguments in txrx functions to bit flags Trent Piepho
[not found] ` <1364905195-24286-3-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-04-02 23:24 ` Marek Vasut [this message]
2013-04-02 12:19 ` [PATCH V2 04/12] spi/mxs: Fix extra CS pulses and read mode in multi-transfer messages Trent Piepho
2013-04-02 12:19 ` [PATCH V2 05/12] spi/mxs: Fix chip select control bits in DMA mode Trent Piepho
[not found] ` <1364905195-24286-5-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-04-02 23:29 ` Marek Vasut
2013-04-02 12:19 ` [PATCH V2 06/12] spi/mxs: Remove full duplex check, spi core already does it Trent Piepho
2013-04-02 12:19 ` [PATCH V2 07/12] spi/mxs: Remove bogus setting of ssp clk rate field Trent Piepho
2013-04-02 12:19 ` [PATCH V2 08/12] spi/mxs: Fix race in setup method Trent Piepho
[not found] ` <1364905195-24286-8-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-04-02 23:31 ` Marek Vasut
[not found] ` <201304030131.37782.marex-ynQEQJNshbs@public.gmane.org>
2013-04-03 2:12 ` Trent Piepho
2013-04-03 2:27 ` Marek Vasut
[not found] ` <201304030427.41297.marex-ynQEQJNshbs@public.gmane.org>
2013-04-03 6:08 ` Trent Piepho
[not found] ` <CA+7tXih2r6YFE80y7z7Nj7c0Ytvh+v56-SrbS+VQ7kCW3KBRXA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-04-03 6:50 ` Marek Vasut
[not found] ` <201304030850.31752.marex-ynQEQJNshbs@public.gmane.org>
2013-04-03 9:32 ` Trent Piepho
2013-04-02 12:19 ` [PATCH V2 09/12] spi/mxs: Remove check of spi mode bits Trent Piepho
2013-04-02 12:19 ` [PATCH V2 10/12] spi/mxs: Clean up setup_transfer function Trent Piepho
[not found] ` <1364905195-24286-10-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-04-02 23:35 ` Marek Vasut
2013-04-02 12:19 ` [PATCH V2 11/12] spi/mxs: Don't set clock for each xfer Trent Piepho
[not found] ` <1364905195-24286-11-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-04-02 23:38 ` Marek Vasut
2013-04-02 12:19 ` [PATCH V2 12/12] spi/mxs: Use u32 instead of uint32_t Trent Piepho
2013-04-02 23:18 ` [PATCH V2 01/12] spi/mxs: Always set LOCK_CS Marek Vasut
[not found] ` <201304030118.42976.marex-ynQEQJNshbs@public.gmane.org>
2013-07-10 13:49 ` Fabio Estevam
2013-07-10 15:29 ` Lothar Waßmann
[not found] ` <20957.32214.721252.361301-VjFSrY7JcPWvSplVBqRQBQ@public.gmane.org>
2013-07-18 1:08 ` Trent Piepho
2013-04-03 1:41 ` Shawn Guo
2013-04-14 18:01 ` Marek Vasut
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