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From: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>
To: Trent Piepho <tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Fabio Estevam
	<fabio.estevam-KZfg59tc24xl57MIdRCFDg@public.gmane.org>,
	spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org,
	Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [PATCH V2 05/12] spi/mxs: Fix chip select control bits in DMA mode
Date: Wed, 3 Apr 2013 01:29:41 +0200	[thread overview]
Message-ID: <201304030129.41380.marex@denx.de> (raw)
In-Reply-To: <1364905195-24286-5-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Dear Trent Piepho,

> In DMA mode the chip select control bits would be ORed into the CTRL0
> register without first clearing the bits.  This means that after
> addressing slave 1 the bit would be still be set when addressing slave
> 0, resulting in slave 1 continuing to be addressed.
> 
> The message handing function would pass the cs value to the txrx
> function, which would re-program the bits on each transfer in the
> message.  The selected cs does not change during a message so this is
> inefficient.  It also means there are two different sets of code for
> selecting the CS, one for PIO that worked and one for DMA that didn't.
> 
> Change the code to set the CS bits in the message transfer function
> once.  Now the DMA and PIO txrx functions don't need to care about CS
> at all.
> 
> Signed-off-by: Trent Piepho <tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>
> Cc: Fabio Estevam <fabio.estevam-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> Cc: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

[...]

> @@ -409,9 +396,12 @@ static int mxs_spi_transfer_one(struct spi_master
> *master, struct spi_transfer *t, *tmp_t;
>  	unsigned int flag;
>  	int status = 0;
> -	int cs;
> 
> -	cs = m->spi->chip_select;
> +	/* Program CS register bits here, it will be used for all transfers. */
> +	writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
> +	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
> +	writel(mxs_spi_cs_to_reg(m->spi->chip_select),
> +	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

I have no problem with this patch in general, but put this stuff back into a 
function with proper description stating that these bits are not what their name 
means. Having this stuff in the code just like that looks like hell and is 
absolutely not clear about what it really does. Besides, having such things well 
encapsulated makes further hacking on/maintainance of the driver much easier.

>  	list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
> 

[...]
Best regards,
Marek Vasut

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  parent reply	other threads:[~2013-04-02 23:29 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-04-02 12:19 [PATCH V2 01/12] spi/mxs: Always set LOCK_CS Trent Piepho
     [not found] ` <1364905195-24286-1-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-04-02 12:19   ` [PATCH V2 02/12] spi/mxs: Remove mxs_spi_enable and mxs_spi_disable Trent Piepho
2013-04-02 12:19   ` [PATCH V2 03/12] spi/mxs: Change flag arguments in txrx functions to bit flags Trent Piepho
     [not found]     ` <1364905195-24286-3-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-04-02 23:24       ` Marek Vasut
2013-04-02 12:19   ` [PATCH V2 04/12] spi/mxs: Fix extra CS pulses and read mode in multi-transfer messages Trent Piepho
2013-04-02 12:19   ` [PATCH V2 05/12] spi/mxs: Fix chip select control bits in DMA mode Trent Piepho
     [not found]     ` <1364905195-24286-5-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-04-02 23:29       ` Marek Vasut [this message]
2013-04-02 12:19   ` [PATCH V2 06/12] spi/mxs: Remove full duplex check, spi core already does it Trent Piepho
2013-04-02 12:19   ` [PATCH V2 07/12] spi/mxs: Remove bogus setting of ssp clk rate field Trent Piepho
2013-04-02 12:19   ` [PATCH V2 08/12] spi/mxs: Fix race in setup method Trent Piepho
     [not found]     ` <1364905195-24286-8-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-04-02 23:31       ` Marek Vasut
     [not found]         ` <201304030131.37782.marex-ynQEQJNshbs@public.gmane.org>
2013-04-03  2:12           ` Trent Piepho
2013-04-03  2:27             ` Marek Vasut
     [not found]               ` <201304030427.41297.marex-ynQEQJNshbs@public.gmane.org>
2013-04-03  6:08                 ` Trent Piepho
     [not found]                   ` <CA+7tXih2r6YFE80y7z7Nj7c0Ytvh+v56-SrbS+VQ7kCW3KBRXA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-04-03  6:50                     ` Marek Vasut
     [not found]                       ` <201304030850.31752.marex-ynQEQJNshbs@public.gmane.org>
2013-04-03  9:32                         ` Trent Piepho
2013-04-02 12:19   ` [PATCH V2 09/12] spi/mxs: Remove check of spi mode bits Trent Piepho
2013-04-02 12:19   ` [PATCH V2 10/12] spi/mxs: Clean up setup_transfer function Trent Piepho
     [not found]     ` <1364905195-24286-10-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-04-02 23:35       ` Marek Vasut
2013-04-02 12:19   ` [PATCH V2 11/12] spi/mxs: Don't set clock for each xfer Trent Piepho
     [not found]     ` <1364905195-24286-11-git-send-email-tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-04-02 23:38       ` Marek Vasut
2013-04-02 12:19   ` [PATCH V2 12/12] spi/mxs: Use u32 instead of uint32_t Trent Piepho
2013-04-02 23:18 ` [PATCH V2 01/12] spi/mxs: Always set LOCK_CS Marek Vasut
     [not found]   ` <201304030118.42976.marex-ynQEQJNshbs@public.gmane.org>
2013-07-10 13:49     ` Fabio Estevam
2013-07-10 15:29       ` Lothar Waßmann
     [not found]         ` <20957.32214.721252.361301-VjFSrY7JcPWvSplVBqRQBQ@public.gmane.org>
2013-07-18  1:08           ` Trent Piepho
2013-04-03  1:41 ` Shawn Guo
2013-04-14 18:01 ` Marek Vasut

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