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* [PATCH 01/13] spi: spi-mxs: Always set LOCK_CS
@ 2013-10-01 20:14 Trent Piepho
  2013-10-01 20:14 ` [PATCH 02/13] spi: spi-mxs: Remove mxs_spi_enable and mxs_spi_disable Trent Piepho
                   ` (12 more replies)
  0 siblings, 13 replies; 14+ messages in thread
From: Trent Piepho @ 2013-10-01 20:14 UTC (permalink / raw)
  To: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f, Mark Brown
  Cc: Marek Vasut, Fabio Estevam, Shawn Guo

There are two bits which control the CS line in the CTRL0 register:
LOCK_CS and IGNORE_CRC.  The latter would be better named DEASSERT_CS
in SPI mode.

LOCK_CS keeps CS asserted though the entire transfer.  This should
always be set.  The DMA code will always set it, explicitly on the
first segment of the first transfer, and then implicitly on all the
rest by never clearing the bit from the value read from the ctrl0
register.

The PIO code will explicitly set it for the first transfer, leave it
set for intermediate transfers, and then clear it for the final
transfer.  It should not clear it.

The only reason to not set LOCK_CS would be to attempt an altered
protocol where CS pulses between each word.  Though don't get your
hopes up if you want to do this, as the hardware doesn't appear to do
this in any sane manner.  It appears to be related to the hardware
FIFO fill level.

The code can be simplified by just setting LOCK_CS once and then not
needing to deal with it at all in the PIO and DMA transfer functions.

Signed-off-by: Trent Piepho <tpiepho-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>
Cc: Fabio Estevam <fabio.estevam-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Cc: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
 drivers/spi/spi-mxs.c |    8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index de7b114..e6172ae 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -79,6 +79,8 @@ static int mxs_spi_setup_transfer(struct spi_device *dev,
 
 	mxs_ssp_set_clk_rate(ssp, hz);
 
+	writel(BM_SSP_CTRL0_LOCK_CS,
+		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
 		     BF_SSP_CTRL1_WORD_LENGTH
 		     (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
@@ -147,8 +149,6 @@ static inline void mxs_spi_enable(struct mxs_spi *spi)
 {
 	struct mxs_ssp *ssp = &spi->ssp;
 
-	writel(BM_SSP_CTRL0_LOCK_CS,
-		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 	writel(BM_SSP_CTRL0_IGNORE_CRC,
 		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
 }
@@ -157,8 +157,6 @@ static inline void mxs_spi_disable(struct mxs_spi *spi)
 {
 	struct mxs_ssp *ssp = &spi->ssp;
 
-	writel(BM_SSP_CTRL0_LOCK_CS,
-		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
 	writel(BM_SSP_CTRL0_IGNORE_CRC,
 		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 }
@@ -232,8 +230,6 @@ static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs,
 	ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
 	ctrl0 |= BM_SSP_CTRL0_DATA_XFER | mxs_spi_cs_to_reg(cs);
 
-	if (*first)
-		ctrl0 |= BM_SSP_CTRL0_LOCK_CS;
 	if (!write)
 		ctrl0 |= BM_SSP_CTRL0_READ;
 


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^ permalink raw reply related	[flat|nested] 14+ messages in thread
end of thread, other threads:[~2013-10-03 16:02 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-10-01 20:14 [PATCH 01/13] spi: spi-mxs: Always set LOCK_CS Trent Piepho
2013-10-01 20:14 ` [PATCH 02/13] spi: spi-mxs: Remove mxs_spi_enable and mxs_spi_disable Trent Piepho
2013-10-01 20:14 ` [PATCH 03/13] spi: spi-mxs: Always clear INGORE_CRC, to keep CS asserted Trent Piepho
2013-10-01 20:14 ` [PATCH 04/13] spi: spi-mxs: Change flag arguments in txrx functions to bit flags Trent Piepho
2013-10-01 20:14 ` [PATCH 05/13] spi: spi-mxs: Fix extra CS pulses and read mode in multi-transfer messages Trent Piepho
2013-10-01 20:15 ` [PATCH 06/13] spi: spi-mxs: Fix chip select control bits in DMA mode Trent Piepho
2013-10-01 20:15 ` [PATCH 07/13] spi: spi-mxs: Remove full duplex check, spi core already does it Trent Piepho
2013-10-01 20:15 ` [PATCH 08/13] spi: spi-mxs: Remove bogus setting of ssp clk rate field Trent Piepho
2013-10-01 20:15 ` [PATCH 09/13] spi: spi-mxs: Fix race in setup method Trent Piepho
2013-10-01 20:15 ` [PATCH 10/13] spi: spi-mxs: Remove check of spi mode bits Trent Piepho
2013-10-01 20:15 ` [PATCH 11/13] spi: spi-mxs: Clean up setup_transfer function Trent Piepho
2013-10-01 20:15 ` [PATCH 12/13] spi: spi-mxs: Don't set clock for each xfer Trent Piepho
2013-10-01 20:15 ` [PATCH 13/13] spi: spi-mxs: Use u32 instead of uint32_t Trent Piepho
2013-10-03 16:02 ` [PATCH 01/13] spi: spi-mxs: Always set LOCK_CS Marek Vasut

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