[PATCH v2 0/3] xtensa xtfpga SPI controller driver

[PATCH v2 0/3] xtensa xtfpga SPI controller driver

[Max Filippov]

Hello,

this series adds driver for SPI controller used on xtfpga xtensa platform,
device tree binding documentation and an entry to MAINTAINERS.

Changes v1 -> v2:
- support 8 bit transfers;
- busy-wait for maximum 100 usec (instead of 100 msec) polling BUSY register;
- use chipselect callback to check transfer size.

Max Filippov (3):
  spi: add xtfpga SPI controller driver
  spi/xtensa-xtfpga: add DT binding documentation
  MAINTAINERS: add xtfpga platform section

 .../devicetree/bindings/spi/spi-xtensa-xtfpga.txt  |   9 +
 MAINTAINERS                                        |   6 +
 drivers/spi/Kconfig                                |  13 ++
 drivers/spi/Makefile                               |   1 +
 drivers/spi/spi-xtensa-xtfpga.c                    | 187 +++++++++++++++++++++
 5 files changed, 216 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt
 create mode 100644 drivers/spi/spi-xtensa-xtfpga.c

-- 
1.8.1.4

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[PATCH v2 1/3] spi: add xtfpga SPI controller driver

[Max Filippov]

This simple SPI master controller is built into xtfpga bitstreams. It
always transfers 16 bit words in SPI mode 0, automatically asserting CS
on transfer start and deasserting on end.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
Changes v1 -> v2:
- support 8 bit transfers;
- busy-wait for maximum 100 usec (instead of 100 msec) polling BUSY register;
- use chipselect callback to check transfer size.

 drivers/spi/Kconfig             |  13 +++
 drivers/spi/Makefile            |   1 +
 drivers/spi/spi-xtensa-xtfpga.c | 187 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 201 insertions(+)
 create mode 100644 drivers/spi/spi-xtensa-xtfpga.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 581ee2a..e3f5335 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -520,6 +520,19 @@ config SPI_XILINX
 
 	  Or for the DS570, see "XPS Serial Peripheral Interface (SPI) (v2.00b)"
 
+config SPI_XTENSA_XTFPGA
+	tristate "Xtensa SPI controller for xtfpga"
+	depends on XTENSA && XTENSA_PLATFORM_XTFPGA
+	select SPI_BITBANG
+	help
+	  SPI driver for xtfpga SPI master controller.
+
+	  This simple SPI master controller is built into xtfpga bitstreams
+	  and is used to control daughterboard audio codec. It always transfers
+	  16 bit words in SPI mode 0, automatically asserting CS on transfer
+	  start and deasserting on end.
+
+
 config SPI_NUC900
 	tristate "Nuvoton NUC900 series SPI"
 	depends on ARCH_W90X900
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 95af48d..5379ade 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -79,3 +79,4 @@ obj-$(CONFIG_SPI_TOPCLIFF_PCH)		+= spi-topcliff-pch.o
 obj-$(CONFIG_SPI_TXX9)			+= spi-txx9.o
 obj-$(CONFIG_SPI_XCOMM)		+= spi-xcomm.o
 obj-$(CONFIG_SPI_XILINX)		+= spi-xilinx.o
+obj-$(CONFIG_SPI_XTENSA_XTFPGA)		+= spi-xtensa-xtfpga.o
diff --git a/drivers/spi/spi-xtensa-xtfpga.c b/drivers/spi/spi-xtensa-xtfpga.c
new file mode 100644
index 0000000..3621162
--- /dev/null
+++ b/drivers/spi/spi-xtensa-xtfpga.c
@@ -0,0 +1,187 @@
+/*
+ * Xtensa xtfpga SPI controller driver
+ *
+ * Copyright (c) 2014 Cadence Design Systems Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_bitbang.h>
+
+#define XTFPGA_SPI_NAME "xtfpga_spi"
+
+#define XTFPGA_SPI_START	0x0
+#define XTFPGA_SPI_BUSY		0x4
+#define XTFPGA_SPI_DATA		0x8
+
+#define BUSY_WAIT_US		100
+
+struct xtfpga_spi {
+	struct spi_bitbang bitbang;
+	void __iomem *regs;
+	u32 data;
+	unsigned data_sz;
+};
+
+static inline void xtfpga_spi_write32(const struct xtfpga_spi *spi,
+				      unsigned addr, u32 val)
+{
+	iowrite32(val, spi->regs + addr);
+}
+
+static inline unsigned int xtfpga_spi_read32(const struct xtfpga_spi *spi,
+					     unsigned addr)
+{
+	return ioread32(spi->regs + addr);
+}
+
+static inline void xtfpga_spi_wait_busy(struct xtfpga_spi *xspi)
+{
+	unsigned i;
+	for (i = 0; xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY) &&
+	     i < BUSY_WAIT_US; ++i)
+		udelay(1);
+	WARN_ON_ONCE(i == BUSY_WAIT_US);
+}
+
+static u32 xtfpga_spi_txrx_word(struct spi_device *spi, unsigned nsecs,
+				u32 v, u8 bits)
+{
+	struct xtfpga_spi *xspi = spi_master_get_devdata(spi->master);
+
+	switch (bits) {
+	case 8:
+		xspi->data = (xspi->data << 8) | (v & 0xff);
+		++xspi->data_sz;
+		break;
+
+	case 16:
+		/* Bytes that should go out earlier have lower addresses,
+		 * but the hardware operates with 16 bit words and transmits
+		 * higher bits first. Thus data in memory is in BE order.
+		 */
+		xspi->data = (xspi->data << 16) | be16_to_cpu(v);
+		xspi->data_sz += 2;
+		break;
+
+	default:
+		WARN(1, "Unsupported word width: %u", bits);
+		break;
+	}
+	if (xspi->data_sz >= 2) {
+		xtfpga_spi_write32(xspi, XTFPGA_SPI_DATA,
+				   xspi->data >> (xspi->data_sz - 2) * 8);
+		xspi->data_sz -= 2;
+		xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 1);
+		xtfpga_spi_wait_busy(xspi);
+		xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 0);
+	}
+
+	return 0;
+}
+
+static void xtfpga_spi_chipselect(struct spi_device *spi, int is_on)
+{
+	struct xtfpga_spi *xspi = spi_master_get_devdata(spi->master);
+
+	WARN_ON(xspi->data_sz != 0);
+	xspi->data_sz = 0;
+}
+
+static int xtfpga_spi_probe(struct platform_device *pdev)
+{
+	struct xtfpga_spi *xspi;
+	struct resource *mem;
+	int ret;
+	struct spi_master *master;
+
+	master = spi_alloc_master(&pdev->dev, sizeof(struct xtfpga_spi));
+	if (!master)
+		return -ENOMEM;
+
+	master->flags = SPI_MASTER_NO_RX;
+	master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
+	master->bus_num = pdev->dev.id;
+	master->dev.of_node = pdev->dev.of_node;
+
+	xspi = spi_master_get_devdata(master);
+	xspi->bitbang.master = master;
+	xspi->bitbang.chipselect = xtfpga_spi_chipselect;
+	xspi->bitbang.txrx_word[SPI_MODE_0] = xtfpga_spi_txrx_word;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem) {
+		dev_err(&pdev->dev, "No memory resource\n");
+		ret = -ENODEV;
+		goto err;
+	}
+	xspi->regs = devm_ioremap_resource(&pdev->dev, mem);
+	if (IS_ERR(xspi->regs)) {
+		ret = PTR_ERR(xspi->regs);
+		goto err;
+	}
+
+	xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 0);
+	usleep_range(1000, 2000);
+	if (xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY)) {
+		dev_err(&pdev->dev, "Device stuck in busy state\n");
+		ret = -EBUSY;
+		goto err;
+	}
+
+	ret = spi_bitbang_start(&xspi->bitbang);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "spi_bitbang_start failed\n");
+		goto err;
+	}
+
+	platform_set_drvdata(pdev, master);
+	return 0;
+err:
+	spi_master_put(master);
+	return ret;
+}
+
+static int xtfpga_spi_remove(struct platform_device *pdev)
+{
+	struct spi_master *master = platform_get_drvdata(pdev);
+	struct xtfpga_spi *xspi = spi_master_get_devdata(master);
+
+	spi_bitbang_stop(&xspi->bitbang);
+	spi_master_put(master);
+
+	return 0;
+}
+
+MODULE_ALIAS("platform:" XTFPGA_SPI_NAME);
+
+#ifdef CONFIG_OF
+static const struct of_device_id xtfpga_spi_of_match[] = {
+	{ .compatible = "cdns,xtfpga-spi", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, xtfpga_spi_of_match);
+#endif
+
+static struct platform_driver xtfpga_spi_driver = {
+	.probe = xtfpga_spi_probe,
+	.remove = xtfpga_spi_remove,
+	.driver = {
+		.name = XTFPGA_SPI_NAME,
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(xtfpga_spi_of_match),
+	},
+};
+module_platform_driver(xtfpga_spi_driver);
+
+MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>");
+MODULE_DESCRIPTION("xtensa xtfpga SPI driver");
+MODULE_LICENSE("GPL");
-- 
1.8.1.4

Re: [PATCH v2 1/3] spi: add xtfpga SPI controller driver

[Mark Brown]

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On Wed, Mar 12, 2014 at 04:21:03PM +0400, Max Filippov wrote:

> +	case 16:
> +		/* Bytes that should go out earlier have lower addresses,
> +		 * but the hardware operates with 16 bit words and transmits
> +		 * higher bits first. Thus data in memory is in BE order.
> +		 */
> +		xspi->data = (xspi->data << 16) | be16_to_cpu(v);
> +		xspi->data_sz += 2;
> +		break;

Are you sure you need to do this byte swap?  SPI words are big endian so
if you are running on a little endian processor if you are transmitting
16 bit words you should see the data getting swapped on the bus (this is
why I say you should never have more than 8 bits per word for regmap).

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Re: [PATCH v2 1/3] spi: add xtfpga SPI controller driver

[Max Filippov]

On Wed, Mar 12, 2014 at 4:49 PM, Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Wed, Mar 12, 2014 at 04:21:03PM +0400, Max Filippov wrote:
>
>> +     case 16:
>> +             /* Bytes that should go out earlier have lower addresses,
>> +              * but the hardware operates with 16 bit words and transmits
>> +              * higher bits first. Thus data in memory is in BE order.
>> +              */
>> +             xspi->data = (xspi->data << 16) | be16_to_cpu(v);
>> +             xspi->data_sz += 2;
>> +             break;
>
> Are you sure you need to do this byte swap?  SPI words are big endian so
> if you are running on a little endian processor if you are transmitting
> 16 bit words you should see the data getting swapped on the bus (this is
> why I say you should never have more than 8 bits per word for regmap).

Looks like this swap is not needed: I've looked at drivers that set
bits_per_word = 16, they submit data in cpu endianness. Will fix in v3.

-- 
Thanks.
-- Max
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[PATCH v2 2/3] spi/xtensa-xtfpga: add DT binding documentation

[Max Filippov]

Signed-off-by: Max Filippov <jcmvbkbc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt | 9 +++++++++
 1 file changed, 9 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt

diff --git a/Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt b/Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt
new file mode 100644
index 0000000..b6ebe2b
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt
@@ -0,0 +1,9 @@
+Cadence Xtensa XTFPGA platform SPI controller.
+
+This simple SPI master controller is built into xtfpga bitstreams and is used
+to control daughterboard audio codec.
+
+Required properties:
+- compatible: should be "cdns,xtfpga-spi".
+- reg: physical base address of the controller and length of memory mapped
+  region.
-- 
1.8.1.4

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Re: [PATCH v2 2/3] spi/xtensa-xtfpga: add DT binding documentation

[Mark Rutland]

On Wed, Mar 12, 2014 at 12:21:04PM +0000, Max Filippov wrote:
> Signed-off-by: Max Filippov <jcmvbkbc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt | 9 +++++++++
>  1 file changed, 9 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt
> 
> diff --git a/Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt b/Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt
> new file mode 100644
> index 0000000..b6ebe2b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt
> @@ -0,0 +1,9 @@
> +Cadence Xtensa XTFPGA platform SPI controller.
> +
> +This simple SPI master controller is built into xtfpga bitstreams and is used
> +to control daughterboard audio codec.
> +
> +Required properties:
> +- compatible: should be "cdns,xtfpga-spi".

Is that the official name of the block? Nothing more specific?

> +- reg: physical base address of the controller and length of memory mapped
> +  region.

No interrupts?

Otherwise, this looks fine to me.

Cheers,
Mark.
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Re: [PATCH v2 2/3] spi/xtensa-xtfpga: add DT binding documentation

[Max Filippov]

On Wed, Mar 12, 2014 at 7:13 PM, Mark Rutland <mark.rutland@arm.com> wrote:
> On Wed, Mar 12, 2014 at 12:21:04PM +0000, Max Filippov wrote:
>> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
>> ---
>>  Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt | 9 +++++++++
>>  1 file changed, 9 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt
>>
>> diff --git a/Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt b/Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt
>> new file mode 100644
>> index 0000000..b6ebe2b
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt
>> @@ -0,0 +1,9 @@
>> +Cadence Xtensa XTFPGA platform SPI controller.
>> +
>> +This simple SPI master controller is built into xtfpga bitstreams and is used
>> +to control daughterboard audio codec.
>> +
>> +Required properties:
>> +- compatible: should be "cdns,xtfpga-spi".
>
> Is that the official name of the block? Nothing more specific?

There's no official name, so I composed this from the official name
of the platform + the block function. AFAIK there's single version of
this IP block. Marc G., please correct me if I'm wrong.

>> +- reg: physical base address of the controller and length of memory mapped
>> +  region.
>
> No interrupts?

Correct.

> Otherwise, this looks fine to me.

-- 
Thanks.
-- Max

[PATCH v2 3/3] MAINTAINERS: add xtfpga platform section

[Max Filippov]

This section will list xtfpga platform-specific drivers.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
 MAINTAINERS | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index c6d0e93..9f75849 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9768,6 +9768,12 @@ L:	linux-serial@vger.kernel.org
 S:	Maintained
 F:	drivers/tty/serial/uartlite.c
 
+XTENSA XTFPGA PLATFORM SUPPORT
+M:	Max Filippov <jcmvbkbc@gmail.com>
+L:	linux-xtensa@linux-xtensa.org
+S:	Maintained
+F:	drivers/spi/spi-xtensa-xtfpga.c
+
 YAM DRIVER FOR AX.25
 M:	Jean-Paul Roubelat <jpr@f6fbb.org>
 L:	linux-hams@vger.kernel.org
-- 
1.8.1.4