[PATCH v3 0/8] DMAEngine support for sun4i, sun5i & sun7i

[PATCH v3 0/8] DMAEngine support for sun4i, sun5i & sun7i

[Emilio López]

Hi everyone,

As part of Google Summer of Code, I've tasked myself with implementing
DMA support for the earlier Allwinner platforms. This third round of
patches is the result of said effort.

The first patch is the actual driver to support these platforms. Patches
three, four and five add the corresponding DMA node to the sun4i, sun5i
and sun7i device trees.

The second patch, involving the sunxi SPI driver, lets users do SPI
transfers of >=64 bytes by using DMA. Patches six, seven and eight add
the DMA properties to SPI so the first two patches can be used.

All comments and reviews are welcome :)

Thanks!

Emilio

Emilio López (8):
  dma: sun4i: Add support for the DMA engine on sun[457]i SoCs
  spi: sun4i: add DMA support
  ARM: sun4i: dt: Add node to represent the DMA controller
  ARM: sun5i: dt: Add nodes to represent the DMA controllers
  ARM: sun7i: dt: Add node to represent the DMA controller
  ARM: sun4i: dt: enable DMA on SPI
  ARM: sun5i: dt: enable DMA on SPI
  ARM: sun7i: dt: enable DMA on SPI

 .../devicetree/bindings/dma/sun4i-dma.txt          |   46 +
 arch/arm/boot/dts/sun4i-a10.dtsi                   |   16 +
 arch/arm/boot/dts/sun5i-a10s.dtsi                  |   14 +
 arch/arm/boot/dts/sun5i-a13.dtsi                   |   14 +
 arch/arm/boot/dts/sun7i-a20.dtsi                   |   16 +
 drivers/dma/Kconfig                                |   11 +
 drivers/dma/Makefile                               |    1 +
 drivers/dma/sun4i-dma.c                            | 1238 ++++++++++++++++++++
 drivers/spi/spi-sun4i.c                            |  155 ++-
 9 files changed, 1500 insertions(+), 11 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/dma/sun4i-dma.txt
 create mode 100644 drivers/dma/sun4i-dma.c

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[PATCH v3 1/8] dma: sun4i: Add support for the DMA engine on sun[457]i SoCs

[Emilio López]

This patch adds support for the DMA engine present on Allwinner A10,
A13, A10S and A20 SoCs. This engine has two kinds of channels: normal
and dedicated. The main difference is in the mode of operation;
while a single normal channel may be operating at any given time,
dedicated channels may operate simultaneously provided there is no
overlap of source or destination.

Hardware documentation can be found on A10 User Manual (section 12), A13
User Manual (section 14) and A20 User Manual (section 1.12)

Signed-off-by: Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
---

Changes from v2:
 * Faster memcpy
 * Quicker cyclic transfers
 * Address some stylistic and locking comments from Maxime
 * probably some more stuff I'm forgetting

Changes from v1:
 * address comments from Chen-Yu and Maxime
 * fix issue converting bus width
 * switch to using a threaded IRQ instead of a tasklet on
   recommendation from Maxime
 * fix issue setting magic timing parameter for SPI transfers
 * fix an issue with list handling reported by the kbuild 0-DAY robot (thanks!)
 * drop a lot of unused #define
 * probably some more stuff I'm forgetting

 .../devicetree/bindings/dma/sun4i-dma.txt          |   46 +
 drivers/dma/Kconfig                                |   11 +
 drivers/dma/Makefile                               |    1 +
 drivers/dma/sun4i-dma.c                            | 1238 ++++++++++++++++++++
 4 files changed, 1296 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/sun4i-dma.txt
 create mode 100644 drivers/dma/sun4i-dma.c

diff --git a/Documentation/devicetree/bindings/dma/sun4i-dma.txt b/Documentation/devicetree/bindings/dma/sun4i-dma.txt
new file mode 100644
index 0000000..f1634a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/sun4i-dma.txt
@@ -0,0 +1,46 @@
+Allwinner A10 DMA Controller
+
+This driver follows the generic DMA bindings defined in dma.txt.
+
+Required properties:
+
+- compatible:	Must be "allwinner,sun4i-a10-dma"
+- reg:		Should contain the registers base address and length
+- interrupts:	Should contain a reference to the interrupt used by this device
+- clocks:	Should contain a reference to the parent AHB clock
+- #dma-cells :	Should be 2, first cell denoting normal or dedicated dma,
+		second cell holding the request line number.
+
+Example:
+	dma: dma-controller@01c02000 {
+		compatible = "allwinner,sun4i-a10-dma";
+		reg = <0x01c02000 0x1000>;
+		interrupts = <27>;
+		clocks = <&ahb_gates 6>;
+		#dma-cells = <2>;
+	};
+
+Clients:
+
+DMA clients connected to the Allwinner A10 DMA controller must use the
+format described in the dma.txt file, using a three-cell specifier for
+each channel: a phandle plus two integer cells.
+The three cells in order are:
+
+1. A phandle pointing to the DMA controller.
+2. Whether it is using normal (0) or dedicated (1) channels
+3. The port ID as specified in the datasheet
+
+Example:
+	spi2: spi@01c17000 {
+		compatible = "allwinner,sun4i-a10-spi";
+		reg = <0x01c17000 0x1000>;
+		interrupts = <0 12 4>;
+		clocks = <&ahb_gates 22>, <&spi2_clk>;
+		clock-names = "ahb", "mod";
+		dmas = <&dma 1 29>, <&dma 1 28>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 1eca7b9..afb8896 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -375,6 +375,17 @@ config XILINX_VDMA
 	  channels, Memory Mapped to Stream (MM2S) and Stream to
 	  Memory Mapped (S2MM) for the data transfers.
 
+config SUN4I_DMA
+	tristate "Allwinner A10 DMA support"
+	depends on (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || (COMPILE_TEST && OF && ARM))
+	default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
+	select DMA_ENGINE
+	select DMA_OF
+	select DMA_VIRTUAL_CHANNELS
+	help
+	  Enable support for the DMA controller present in the sun4i,
+	  sun5i and sun7i Allwinner ARM SoCs.
+
 config DMA_ENGINE
 	bool
 
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index c779e1e..430de61 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -47,3 +47,4 @@ obj-$(CONFIG_MOXART_DMA) += moxart-dma.o
 obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
 obj-$(CONFIG_QCOM_BAM_DMA) += qcom_bam_dma.o
 obj-y += xilinx/
+obj-$(CONFIG_SUN4I_DMA) += sun4i-dma.o
diff --git a/drivers/dma/sun4i-dma.c b/drivers/dma/sun4i-dma.c
new file mode 100644
index 0000000..f023aa4
--- /dev/null
+++ b/drivers/dma/sun4i-dma.c
@@ -0,0 +1,1238 @@
+/*
+ * Copyright (C) 2014 Emilio López
+ * Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/dmaengine.h>
+#include <linux/dmapool.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of_dma.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include "virt-dma.h"
+
+/** Normal DMA register values **/
+
+/* Normal DMA source/destination data request type values */
+#define NDMA_DRQ_TYPE_SDRAM			0x16
+#define NDMA_DRQ_TYPE_LIMIT			(0x1F + 1)
+
+/** Normal DMA register layout **/
+
+/* Normal DMA configuration register layout */
+#define NDMA_CFG_LOADING			BIT(31)
+#define NDMA_CFG_CONT_MODE			BIT(30)
+#define NDMA_CFG_WAIT_STATE(n)			((n) << 27)
+#define NDMA_CFG_DEST_DATA_WIDTH(width)		((width) << 25)
+#define NDMA_CFG_DEST_BURST_LENGTH(len)		((len) << 23)
+#define NDMA_CFG_DEST_NON_SECURE		BIT(22)
+#define NDMA_CFG_DEST_FIXED_ADDR		BIT(21)
+#define NDMA_CFG_DEST_DRQ_TYPE(type)		((type) << 16)
+#define NDMA_CFG_BYTE_COUNT_MODE_REMAIN		BIT(15)
+#define NDMA_CFG_SRC_DATA_WIDTH(width)		((width) << 9)
+#define NDMA_CFG_SRC_BURST_LENGTH(len)		((len) << 7)
+#define NDMA_CFG_SRC_NON_SECURE			BIT(6)
+#define NDMA_CFG_SRC_FIXED_ADDR			BIT(5)
+#define NDMA_CFG_SRC_DRQ_TYPE(type)		((type) << 0)
+
+/** Dedicated DMA register values **/
+
+/* Dedicated DMA source/destination address mode values */
+#define DDMA_ADDR_MODE_LINEAR			0
+#define DDMA_ADDR_MODE_IO			1
+#define DDMA_ADDR_MODE_HORIZONTAL_PAGE		2
+#define DDMA_ADDR_MODE_VERTICAL_PAGE		3
+
+/* Dedicated DMA source/destination data request type values */
+#define DDMA_DRQ_TYPE_SDRAM			0x1
+#define DDMA_DRQ_TYPE_LIMIT			(0x1F + 1)
+
+/** Dedicated DMA register layout **/
+
+/* Dedicated DMA configuration register layout */
+#define DDMA_CFG_LOADING			BIT(31)
+#define DDMA_CFG_BUSY				BIT(30)
+#define DDMA_CFG_CONT_MODE			BIT(29)
+#define DDMA_CFG_DEST_NON_SECURE		BIT(28)
+#define DDMA_CFG_DEST_DATA_WIDTH(width)		((width) << 25)
+#define DDMA_CFG_DEST_BURST_LENGTH(len)		((len) << 23)
+#define DDMA_CFG_DEST_ADDR_MODE(mode)		((mode) << 21)
+#define DDMA_CFG_DEST_DRQ_TYPE(type)		((type) << 16)
+#define DDMA_CFG_BYTE_COUNT_MODE_REMAIN		BIT(15)
+#define DDMA_CFG_SRC_NON_SECURE			BIT(12)
+#define DDMA_CFG_SRC_DATA_WIDTH(width)		((width) << 9)
+#define DDMA_CFG_SRC_BURST_LENGTH(len)		((len) << 7)
+#define DDMA_CFG_SRC_ADDR_MODE(mode)		((mode) << 5)
+#define DDMA_CFG_SRC_DRQ_TYPE(type)		((type) << 0)
+
+/* Dedicated DMA parameter register layout */
+#define DDMA_PARA_DEST_DATA_BLK_SIZE(n)		(((n) - 1) << 24)
+#define DDMA_PARA_DEST_WAIT_CYCLES(n)		(((n) - 1) << 16)
+#define DDMA_PARA_SRC_DATA_BLK_SIZE(n)		(((n) - 1) << 8)
+#define DDMA_PARA_SRC_WAIT_CYCLES(n)		(((n) - 1) << 0)
+
+/** DMA register offsets **/
+
+/* General register offsets */
+#define DMA_IRQ_ENABLE_REG			0x0
+#define DMA_IRQ_PENDING_STATUS_REG		0x4
+
+/* Normal DMA register offsets */
+#define NDMA_CHANNEL_REG_BASE(n)		(0x100 + (n) * 0x20)
+#define NDMA_CFG_REG				0x0
+#define NDMA_SRC_ADDR_REG			0x4
+#define NDMA_DEST_ADDR_REG			0x8
+#define NDMA_BYTE_COUNT_REG			0xC
+
+/* Dedicated DMA register offsets */
+#define DDMA_CHANNEL_REG_BASE(n)		(0x300 + (n) * 0x20)
+#define DDMA_CFG_REG				0x0
+#define DDMA_SRC_ADDR_REG			0x4
+#define DDMA_DEST_ADDR_REG			0x8
+#define DDMA_BYTE_COUNT_REG			0xC
+#define DDMA_PARA_REG				0x18
+
+/** DMA Driver **/
+
+/*
+ * Normal DMA has 8 channels, and Dedicated DMA has another 8, so that's
+ * 16 channels. As for endpoints, there's 29 and 21 respectively. Given
+ * that the Normal DMA endpoints (other than SDRAM) can be used as tx/rx,
+ * we need 78 vchans in total
+ */
+#define NDMA_NR_MAX_CHANNELS	8
+#define DDMA_NR_MAX_CHANNELS	8
+#define DMA_NR_MAX_CHANNELS	(NDMA_NR_MAX_CHANNELS + DDMA_NR_MAX_CHANNELS)
+#define NDMA_NR_MAX_VCHANS	(29 * 2 - 1)
+#define DDMA_NR_MAX_VCHANS	21
+#define DMA_NR_MAX_VCHANS	(NDMA_NR_MAX_VCHANS + DDMA_NR_MAX_VCHANS)
+
+/* This set of DDMA timing parameters were found experimentally while
+ * working with the SPI driver and seem to make it behave correctly */
+#define DDMA_MAGIC_SPI_PARAMETERS	(DDMA_PARA_DEST_DATA_BLK_SIZE(1) | \
+					DDMA_PARA_SRC_DATA_BLK_SIZE(1) | \
+					DDMA_PARA_DEST_WAIT_CYCLES(2) | \
+					DDMA_PARA_SRC_WAIT_CYCLES(2))
+
+struct sun4i_dma_pchan {
+	/* Register base of channel */
+	void __iomem			*base;
+	/* vchan currently being serviced */
+	struct sun4i_dma_vchan		*vchan;
+	/* Is this a dedicated pchan? */
+	int				is_dedicated;
+};
+
+struct sun4i_dma_vchan {
+	struct virt_dma_chan		vc;
+	struct dma_slave_config		cfg;
+	struct sun4i_dma_pchan		*pchan;
+	struct sun4i_dma_promise	*processing;
+	struct sun4i_dma_contract	*contract;
+	u8				endpoint;
+	int				is_dedicated;
+};
+
+struct sun4i_dma_promise {
+	u32				cfg;
+	u32				para;
+	dma_addr_t			src;
+	dma_addr_t			dst;
+	size_t				len;
+	struct list_head		list;
+};
+
+/* A contract is a set of promises */
+struct sun4i_dma_contract {
+	struct virt_dma_desc		vd;
+	struct list_head		demands;
+	struct list_head		completed_demands;
+	int				is_cyclic;
+};
+
+struct sun4i_dma_dev {
+	DECLARE_BITMAP(pchans_used, DMA_NR_MAX_CHANNELS);
+	struct dma_device		slave;
+	struct sun4i_dma_pchan		*pchans;
+	struct sun4i_dma_vchan		*vchans;
+	void __iomem			*base;
+	struct clk			*clk;
+	int				irq;
+	spinlock_t			lock;
+};
+
+static struct sun4i_dma_dev *to_sun4i_dma_dev(struct dma_device *dev)
+{
+	return container_of(dev, struct sun4i_dma_dev, slave);
+}
+
+static struct sun4i_dma_vchan *to_sun4i_dma_vchan(struct dma_chan *chan)
+{
+	return container_of(chan, struct sun4i_dma_vchan, vc.chan);
+}
+
+static struct sun4i_dma_contract *to_sun4i_dma_contract(struct virt_dma_desc *vd)
+{
+	return container_of(vd, struct sun4i_dma_contract, vd);
+}
+
+static struct device *chan2dev(struct dma_chan *chan)
+{
+	return &chan->dev->device;
+}
+
+static int convert_burst(u32 maxburst)
+{
+	if (maxburst > 8)
+		return -EINVAL;
+
+	/* 1 -> 0, 4 -> 1, 8 -> 2 */
+	return (maxburst >> 2);
+}
+
+static int convert_buswidth(enum dma_slave_buswidth addr_width)
+{
+	if (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES)
+		return -EINVAL;
+
+	/* 8 (1 byte) -> 0, 16 (2 bytes) -> 1, 32 (4 bytes) -> 2 */
+	return (addr_width >> 1);
+}
+
+static int choose_optimal_buswidth(dma_addr_t addr)
+{
+	/* On 32 bit aligned addresses, we can use a 32 bit bus width */
+	if (addr % 4 == 0)
+		return DMA_SLAVE_BUSWIDTH_4_BYTES;
+	/* On 16 bit aligned addresses, we can use a 16 bit bus width */
+	else if (addr % 2 == 0)
+		return DMA_SLAVE_BUSWIDTH_2_BYTES;
+
+	/* Worst-case scenario, we need to do byte aligned reads */
+	return DMA_SLAVE_BUSWIDTH_1_BYTE;
+}
+
+static int sun4i_dma_alloc_chan_resources(struct dma_chan *chan)
+{
+	return 0;
+}
+
+static void sun4i_dma_free_chan_resources(struct dma_chan *chan)
+{
+	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
+
+	vchan_free_chan_resources(&vchan->vc);
+}
+
+static struct sun4i_dma_pchan *find_and_use_pchan(struct sun4i_dma_dev *priv,
+						  struct sun4i_dma_vchan *vchan)
+{
+	struct sun4i_dma_pchan *pchan = NULL, *pchans = priv->pchans;
+	unsigned long flags;
+	int i, max;
+
+	/*
+	 * pchans 0-NDMA_NR_MAX_CHANNELS are normal, and
+	 * NDMA_NR_MAX_CHANNELS+ are dedicated ones
+	 */
+	if (vchan->is_dedicated) {
+		i = NDMA_NR_MAX_CHANNELS;
+		max = DMA_NR_MAX_CHANNELS;
+	} else {
+		i = 0;
+		max = NDMA_NR_MAX_CHANNELS;
+	}
+
+	spin_lock_irqsave(&priv->lock, flags);
+	for_each_clear_bit_from(i, &priv->pchans_used, max) {
+		pchan = &pchans[i];
+		pchan->vchan = vchan;
+		set_bit(i, priv->pchans_used);
+		break;
+	}
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	return pchan;
+}
+
+static void release_pchan(struct sun4i_dma_dev *priv,
+			  struct sun4i_dma_pchan *pchan)
+{
+	unsigned long flags;
+	int nr = pchan - priv->pchans;
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	clear_bit(nr, priv->pchans_used);
+	pchan->vchan = NULL;
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+}
+
+static void configure_pchan(struct sun4i_dma_pchan *pchan,
+			    struct sun4i_dma_promise *d)
+{
+	/*
+	 * Configure addresses and misc parameters depending on type
+	 * DDMA has an extra field with timing parameters
+	 */
+	if (pchan->is_dedicated) {
+		writel_relaxed(d->src, pchan->base + DDMA_SRC_ADDR_REG);
+		writel_relaxed(d->dst, pchan->base + DDMA_DEST_ADDR_REG);
+		writel_relaxed(d->len, pchan->base + DDMA_BYTE_COUNT_REG);
+		writel_relaxed(d->para, pchan->base + DDMA_PARA_REG);
+		writel_relaxed(d->cfg, pchan->base + DDMA_CFG_REG);
+	} else {
+		writel_relaxed(d->src, pchan->base + NDMA_SRC_ADDR_REG);
+		writel_relaxed(d->dst, pchan->base + NDMA_DEST_ADDR_REG);
+		writel_relaxed(d->len, pchan->base + NDMA_BYTE_COUNT_REG);
+		writel_relaxed(d->cfg, pchan->base + NDMA_CFG_REG);
+	}
+}
+
+static void set_pchan_interrupt(struct sun4i_dma_dev *priv,
+				struct sun4i_dma_pchan *pchan,
+				int half, int end)
+{
+	u32 reg;
+	int pchan_number = pchan - priv->pchans;
+	unsigned long flags;
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	reg = readl_relaxed(priv->base + DMA_IRQ_ENABLE_REG);
+
+	if (half)
+		reg |= BIT(pchan_number * 2);
+	else
+		reg &= ~BIT(pchan_number * 2);
+
+	if (end)
+		reg |= BIT(pchan_number * 2 + 1);
+	else
+		reg &= ~BIT(pchan_number * 2 + 1);
+
+	writel_relaxed(reg, priv->base + DMA_IRQ_ENABLE_REG);
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+}
+
+static int execute_vchan_pending(struct sun4i_dma_dev *priv,
+				 struct sun4i_dma_vchan *vchan)
+{
+	struct sun4i_dma_promise *promise = NULL;
+	struct sun4i_dma_contract *contract = NULL;
+	struct sun4i_dma_pchan *pchan;
+	struct virt_dma_desc *vd;
+	int ret;
+
+	lockdep_assert_held(&vchan->vc.lock);
+
+	/* We need a pchan to do anything, so secure one if available */
+	pchan = find_and_use_pchan(priv, vchan);
+	if (!pchan)
+		return -EBUSY;
+
+	/*
+	 * Channel endpoints must not be repeated, so if this vchan
+	 * has already submitted some work, we can't do anything else
+	 */
+	if (vchan->processing) {
+		dev_dbg(chan2dev(&vchan->vc.chan),
+			"processing something to this endpoint already\n");
+		ret = -EBUSY;
+		goto release_pchan;
+	}
+
+	do {
+		/* Figure out which contract we're working with today */
+		vd = vchan_next_desc(&vchan->vc);
+		if (!vd) {
+			dev_dbg(chan2dev(&vchan->vc.chan),
+				"No pending contract found");
+			ret = 0;
+			goto release_pchan;
+		}
+
+		contract = to_sun4i_dma_contract(vd);
+		if (list_empty(&contract->demands)) {
+			/* The contract has been completed so mark it as such */
+			list_del(&contract->vd.node);
+			vchan_cookie_complete(&contract->vd);
+			dev_dbg(chan2dev(&vchan->vc.chan),
+				"Empty contract found and marked complete");
+		}
+	} while (list_empty(&contract->demands));
+
+	/* Now find out what we need to do */
+	promise = list_first_entry(&contract->demands,
+				   struct sun4i_dma_promise, list);
+	vchan->processing = promise;
+
+	/* ... and make it reality */
+	if (promise) {
+		vchan->contract = contract;
+		vchan->pchan = pchan;
+		set_pchan_interrupt(priv, pchan, contract->is_cyclic, 1);
+		configure_pchan(pchan, promise);
+	}
+
+	return 0;
+
+release_pchan:
+	release_pchan(priv, pchan);
+	return ret;
+}
+
+/**
+ * Generate a promise, to be used in a normal DMA contract.
+ *
+ * A NDMA promise contains all the information required to program the
+ * normal part of the DMA Engine and get data copied. A non-executed
+ * promise will live in the demands list on a contract. Once it has been
+ * completed, it will be moved to the completed demands list for later freeing.
+ * All linked promises will be freed when the corresponding contract is freed
+ */
+static struct sun4i_dma_promise *
+generate_ndma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest,
+		      size_t len, struct dma_slave_config *sconfig)
+{
+	struct sun4i_dma_promise *promise;
+	int ret;
+
+	promise = kzalloc(sizeof(*promise), GFP_NOWAIT);
+	if (!promise)
+		return NULL;
+
+	promise->src = src;
+	promise->dst = dest;
+	promise->len = len;
+	promise->cfg = NDMA_CFG_LOADING | NDMA_CFG_BYTE_COUNT_MODE_REMAIN;
+
+	/* Use sensible default values if client is using undefined ones */
+	if (sconfig->src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
+		sconfig->src_addr_width = sconfig->dst_addr_width;
+	if (sconfig->dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
+		sconfig->dst_addr_width = sconfig->src_addr_width;
+	if (sconfig->src_maxburst == 0)
+		sconfig->src_maxburst = sconfig->dst_maxburst;
+	if (sconfig->dst_maxburst == 0)
+		sconfig->dst_maxburst = sconfig->src_maxburst;
+
+	dev_dbg(chan2dev(chan),
+		"src burst %d, dst burst %d, src buswidth %d, dst buswidth %d",
+		sconfig->src_maxburst, sconfig->dst_maxburst,
+		sconfig->src_addr_width, sconfig->dst_addr_width);
+
+	/* Source burst */
+	ret = convert_burst(sconfig->src_maxburst);
+	if (IS_ERR_VALUE(ret))
+		goto fail;
+	promise->cfg |= NDMA_CFG_SRC_BURST_LENGTH(ret);
+
+	/* Destination burst */
+	ret = convert_burst(sconfig->dst_maxburst);
+	if (IS_ERR_VALUE(ret))
+		goto fail;
+	promise->cfg |= NDMA_CFG_DEST_BURST_LENGTH(ret);
+
+	/* Source bus width */
+	ret = convert_buswidth(sconfig->src_addr_width);
+	if (IS_ERR_VALUE(ret))
+		goto fail;
+	promise->cfg |= NDMA_CFG_SRC_DATA_WIDTH(ret);
+
+	/* Destination bus width */
+	ret = convert_buswidth(sconfig->dst_addr_width);
+	if (IS_ERR_VALUE(ret))
+		goto fail;
+	promise->cfg |= NDMA_CFG_DEST_DATA_WIDTH(ret);
+
+	return promise;
+
+fail:
+	kfree(promise);
+	return NULL;
+}
+
+/**
+ * Generate a promise, to be used in a dedicated DMA contract.
+ *
+ * A DDMA promise contains all the information required to program the
+ * Dedicated part of the DMA Engine and get data copied. A non-executed
+ * promise will live in the demands list on a contract. Once it has been
+ * completed, it will be moved to the completed demands list for later freeing.
+ * All linked promises will be freed when the corresponding contract is freed
+ */
+static struct sun4i_dma_promise *
+generate_ddma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest,
+		      size_t len, struct dma_slave_config *sconfig)
+{
+	struct sun4i_dma_promise *promise;
+	int ret;
+
+	promise = kzalloc(sizeof(*promise), GFP_NOWAIT);
+	if (!promise)
+		return NULL;
+
+	promise->src = src;
+	promise->dst = dest;
+	promise->len = len;
+	promise->cfg = DDMA_CFG_LOADING | DDMA_CFG_BYTE_COUNT_MODE_REMAIN;
+
+	/* Source burst */
+	ret = convert_burst(sconfig->src_maxburst);
+	if (IS_ERR_VALUE(ret))
+		goto fail;
+	promise->cfg |= DDMA_CFG_SRC_BURST_LENGTH(ret);
+
+	/* Destination burst */
+	ret = convert_burst(sconfig->dst_maxburst);
+	if (IS_ERR_VALUE(ret))
+		goto fail;
+	promise->cfg |= DDMA_CFG_DEST_BURST_LENGTH(ret);
+
+	/* Source bus width */
+	ret = convert_buswidth(sconfig->src_addr_width);
+	if (IS_ERR_VALUE(ret))
+		goto fail;
+	promise->cfg |= DDMA_CFG_SRC_DATA_WIDTH(ret);
+
+	/* Destination bus width */
+	ret = convert_buswidth(sconfig->dst_addr_width);
+	if (IS_ERR_VALUE(ret))
+		goto fail;
+	promise->cfg |= DDMA_CFG_DEST_DATA_WIDTH(ret);
+
+	return promise;
+
+fail:
+	kfree(promise);
+	return NULL;
+}
+
+/**
+ * Generate a contract
+ *
+ * Contracts function as DMA descriptors. As our hardware does not support
+ * linked lists, we need to implement SG via software. We use a contract
+ * to hold all the pieces of the request and process them serially one
+ * after another. Each piece is represented as a promise.
+ */
+static struct sun4i_dma_contract *generate_dma_contract(void)
+{
+	struct sun4i_dma_contract *contract;
+
+	contract = kzalloc(sizeof(*contract), GFP_NOWAIT);
+	if (!contract)
+		return NULL;
+
+	INIT_LIST_HEAD(&contract->demands);
+	INIT_LIST_HEAD(&contract->completed_demands);
+
+	return contract;
+}
+
+/**
+ * Get next promise on a cyclic transfer
+ *
+ * Cyclic contracts contain a series of promises which are executed on a
+ * loop. This function returns the next promise from a cyclic contract,
+ * so it can be programmed into the hardware.
+ */
+static struct sun4i_dma_promise *
+get_next_cyclic_promise(struct sun4i_dma_contract *contract)
+{
+	struct sun4i_dma_promise *promise;
+
+	promise = list_first_entry_or_null(&contract->demands,
+					   struct sun4i_dma_promise, list);
+	if (!promise) {
+		list_splice_init(&contract->completed_demands,
+				 &contract->demands);
+		promise = list_first_entry(&contract->demands,
+					   struct sun4i_dma_promise, list);
+	}
+
+	return promise;
+}
+
+/**
+ * Free a contract and all its associated promises
+ */
+static void sun4i_dma_free_contract(struct virt_dma_desc *vd)
+{
+	struct sun4i_dma_contract *contract = to_sun4i_dma_contract(vd);
+	struct sun4i_dma_promise *promise;
+
+	/* Free all the demands and completed demands */
+	list_for_each_entry(promise, &contract->demands, list)
+		kfree(promise);
+
+	list_for_each_entry(promise, &contract->completed_demands, list)
+		kfree(promise);
+
+	kfree(contract);
+}
+
+static struct dma_async_tx_descriptor *
+sun4i_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest,
+			  dma_addr_t src, size_t len, unsigned long flags)
+{
+	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
+	struct dma_slave_config *sconfig = &vchan->cfg;
+	struct sun4i_dma_promise *promise;
+	struct sun4i_dma_contract *contract;
+
+	contract = generate_dma_contract();
+	if (!contract)
+		return NULL;
+
+	/*
+	 * We can only do the copy to bus aligned addresses, so
+	 * choose the best one so we get decent performance. We also
+	 * maximize the burst size for this same reason.
+	 */
+	sconfig->src_addr_width = choose_optimal_buswidth(src);
+	sconfig->dst_addr_width = choose_optimal_buswidth(dest);
+	sconfig->src_maxburst = 8;
+	sconfig->dst_maxburst = 8;
+
+	if (vchan->is_dedicated)
+		promise = generate_ddma_promise(chan, src, dest, len, sconfig);
+	else
+		promise = generate_ndma_promise(chan, src, dest, len, sconfig);
+
+	if (!promise) {
+		kfree(contract);
+		return NULL;
+	}
+
+	/* Configure memcpy mode */
+	if (vchan->is_dedicated) {
+		promise->cfg |= DDMA_CFG_SRC_DRQ_TYPE(DDMA_DRQ_TYPE_SDRAM) |
+				DDMA_CFG_DEST_DRQ_TYPE(DDMA_DRQ_TYPE_SDRAM);
+	} else {
+		promise->cfg |= NDMA_CFG_SRC_DRQ_TYPE(NDMA_DRQ_TYPE_SDRAM) |
+				NDMA_CFG_DEST_DRQ_TYPE(NDMA_DRQ_TYPE_SDRAM);
+	}
+
+	/* Fill the contract with our only promise */
+	list_add_tail(&promise->list, &contract->demands);
+
+	/* And add it to the vchan */
+	return vchan_tx_prep(&vchan->vc, &contract->vd, flags);
+}
+
+static struct dma_async_tx_descriptor *
+sun4i_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf, size_t len,
+			  size_t period_len, enum dma_transfer_direction dir,
+			  unsigned long flags, void *context)
+{
+	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
+	struct dma_slave_config *sconfig = &vchan->cfg;
+	struct sun4i_dma_promise *promise;
+	struct sun4i_dma_contract *contract;
+	dma_addr_t src, dest;
+	u32 endpoints;
+	int nr_periods, offset, plength, i;
+
+	if (!is_slave_direction(dir)) {
+		dev_err(chan2dev(chan), "Invalid DMA direction\n");
+		return NULL;
+	}
+
+	if (vchan->is_dedicated) {
+		/*
+		 * As we are using this just for audio data, we need to use
+		 * normal DMA. There is nothing stopping us from supporting
+		 * dedicated DMA here as well, so if a client comes up and
+		 * requires it, it will be simple to implement it.
+		 */
+		dev_err(chan2dev(chan),
+			"Cyclic transfers are only supported on Normal DMA\n");
+		return NULL;
+	}
+
+	contract = generate_dma_contract();
+	if (!contract)
+		return NULL;
+
+	contract->is_cyclic = 1;
+
+	/* Figure out the endpoints and the address we need */
+	if (dir == DMA_MEM_TO_DEV) {
+		src = buf;
+		dest = sconfig->dst_addr;
+		endpoints = NDMA_CFG_SRC_DRQ_TYPE(NDMA_DRQ_TYPE_SDRAM) |
+			    NDMA_CFG_DEST_DRQ_TYPE(vchan->endpoint) |
+			    NDMA_CFG_DEST_FIXED_ADDR;
+	} else {
+		src = sconfig->src_addr;
+		dest = buf;
+		endpoints = NDMA_CFG_SRC_DRQ_TYPE(vchan->endpoint) |
+			    NDMA_CFG_SRC_FIXED_ADDR |
+			    NDMA_CFG_DEST_DRQ_TYPE(NDMA_DRQ_TYPE_SDRAM);
+	}
+
+	/*
+	 * We will be using half done interrupts to make two periods
+	 * out of a promise, so we need to program the DMA engine less
+	 * often
+	 */
+	nr_periods = DIV_ROUND_UP(len / period_len, 2);
+	for (i = 0; i < nr_periods; i++) {
+		/* Calculate the offset in the buffer and the length needed */
+		offset = i * period_len * 2;
+		plength = min((len - offset), (period_len * 2));
+		if (dir == DMA_MEM_TO_DEV)
+			src = buf + offset;
+		else
+			dest = buf + offset;
+
+		/* Make the promise */
+		promise = generate_ndma_promise(chan, src, dest,
+						plength, sconfig);
+		if (!promise) {
+			/* TODO: should we free everything? */
+			return NULL;
+		}
+		promise->cfg |= endpoints;
+
+		/* Then add it to the contract */
+		list_add_tail(&promise->list, &contract->demands);
+	}
+
+	/* And add it to the vchan */
+	return vchan_tx_prep(&vchan->vc, &contract->vd, flags);
+}
+
+static struct dma_async_tx_descriptor *
+sun4i_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
+			unsigned int sg_len, enum dma_transfer_direction dir,
+			unsigned long flags, void *context)
+{
+	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
+	struct dma_slave_config *sconfig = &vchan->cfg;
+	struct sun4i_dma_promise *promise;
+	struct sun4i_dma_contract *contract;
+	struct scatterlist *sg;
+	dma_addr_t srcaddr, dstaddr;
+	u32 endpoints, para;
+	int i;
+
+	if (!sgl)
+		return NULL;
+
+	if (!is_slave_direction(dir)) {
+		dev_err(chan2dev(chan), "Invalid DMA direction\n");
+		return NULL;
+	}
+
+	contract = generate_dma_contract();
+	if (!contract)
+		return NULL;
+
+	/* Figure out endpoints */
+	if (vchan->is_dedicated && dir == DMA_MEM_TO_DEV) {
+		endpoints = DDMA_CFG_SRC_DRQ_TYPE(DDMA_DRQ_TYPE_SDRAM) |
+			    DDMA_CFG_SRC_ADDR_MODE(DDMA_ADDR_MODE_LINEAR) |
+			    DDMA_CFG_DEST_DRQ_TYPE(vchan->endpoint) |
+			    DDMA_CFG_DEST_ADDR_MODE(DDMA_ADDR_MODE_IO);
+	} else if (!vchan->is_dedicated && dir == DMA_MEM_TO_DEV) {
+		endpoints = NDMA_CFG_SRC_DRQ_TYPE(NDMA_DRQ_TYPE_SDRAM) |
+			    NDMA_CFG_DEST_DRQ_TYPE(vchan->endpoint) |
+			    NDMA_CFG_DEST_FIXED_ADDR;
+	} else if (vchan->is_dedicated) {
+		endpoints = DDMA_CFG_SRC_DRQ_TYPE(vchan->endpoint) |
+			    DDMA_CFG_SRC_ADDR_MODE(DDMA_ADDR_MODE_IO) |
+			    DDMA_CFG_DEST_DRQ_TYPE(DDMA_DRQ_TYPE_SDRAM) |
+			    DDMA_CFG_DEST_ADDR_MODE(DDMA_ADDR_MODE_LINEAR);
+	} else {
+		endpoints = NDMA_CFG_SRC_DRQ_TYPE(vchan->endpoint) |
+			    NDMA_CFG_SRC_FIXED_ADDR |
+			    NDMA_CFG_DEST_DRQ_TYPE(NDMA_DRQ_TYPE_SDRAM);
+	}
+
+	for_each_sg(sgl, sg, sg_len, i) {
+		/* Figure out addresses */
+		if (dir == DMA_MEM_TO_DEV) {
+			srcaddr = sg_dma_address(sg);
+			dstaddr = sconfig->dst_addr;
+		} else {
+			srcaddr = sconfig->src_addr;
+			dstaddr = sg_dma_address(sg);
+		}
+
+		/*
+		 * These are the magic DMA engine timings that keep SPI going.
+		 * I haven't seen any interface on DMAEngine to configure
+		 * timings, and so far they seem to work for everything we
+		 * support, so I've kept them here. I don't know if other
+		 * devices need different timings because, as usual, we only
+		 * have the "para" bitfield meanings, but no comment on what
+		 * the values should be when doing a certain operation :|
+		 */
+		para = DDMA_MAGIC_SPI_PARAMETERS;
+
+		/* And make a suitable promise */
+		if (vchan->is_dedicated)
+			promise = generate_ddma_promise(chan, srcaddr, dstaddr,
+							sg_dma_len(sg), sconfig);
+		else
+			promise = generate_ndma_promise(chan, srcaddr, dstaddr,
+							sg_dma_len(sg), sconfig);
+
+		if (!promise)
+			return NULL; /* TODO: should we free everything? */
+
+		promise->cfg |= endpoints;
+		promise->para = para;
+
+		/* Then add it to the contract */
+		list_add_tail(&promise->list, &contract->demands);
+	}
+
+	/*
+	 * Once we've got all the promises ready, add the contract
+	 * to the pending list on the vchan
+	 */
+	return vchan_tx_prep(&vchan->vc, &contract->vd, flags);
+}
+
+static int sun4i_dma_terminate_all(struct sun4i_dma_dev *priv,
+				   struct sun4i_dma_vchan *vchan)
+{
+	struct sun4i_dma_pchan *pchan = vchan->pchan;
+	LIST_HEAD(head);
+	unsigned long flags;
+
+	spin_lock_irqsave(&vchan->vc.lock, flags);
+	vchan_get_all_descriptors(&vchan->vc, &head);
+	spin_unlock_irqrestore(&vchan->vc.lock, flags);
+
+	/* Clearing the configuration register will halt the pchan */
+	if (pchan) {
+		if (pchan->is_dedicated)
+			writel(0, pchan->base + DDMA_CFG_REG);
+		else
+			writel(0, pchan->base + NDMA_CFG_REG);
+		release_pchan(priv, pchan);
+	}
+
+	spin_lock_irqsave(&vchan->vc.lock, flags);
+	vchan_dma_desc_free_list(&vchan->vc, &head);
+	/* Clear these so the vchan is usable again */
+	vchan->processing = NULL;
+	vchan->pchan = NULL;
+	spin_unlock_irqrestore(&vchan->vc.lock, flags);
+
+	return 0;
+}
+
+static int sun4i_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+			     unsigned long arg)
+{
+	struct sun4i_dma_dev *priv = to_sun4i_dma_dev(chan->device);
+	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
+	int ret = 0;
+
+	switch (cmd) {
+	case DMA_RESUME:
+	case DMA_PAUSE:
+		ret = -EINVAL;
+		break;
+
+	case DMA_TERMINATE_ALL:
+		dev_dbg(chan2dev(chan), "Terminating everything on channel\n");
+		ret = sun4i_dma_terminate_all(priv, vchan);
+		break;
+
+	case DMA_SLAVE_CONFIG:
+		memcpy(&vchan->cfg, (void *)arg, sizeof(vchan->cfg));
+		break;
+
+	default:
+		ret = -ENXIO;
+		break;
+	}
+
+	return ret;
+}
+
+static struct dma_chan *sun4i_dma_of_xlate(struct of_phandle_args *dma_spec,
+					   struct of_dma *ofdma)
+{
+	struct sun4i_dma_dev *priv = ofdma->of_dma_data;
+	struct sun4i_dma_vchan *vchan;
+	struct dma_chan *chan;
+	u8 is_dedicated = dma_spec->args[0];
+	u8 endpoint = dma_spec->args[1];
+
+	/* Check if type is Normal or Dedicated */
+	if (is_dedicated != 0 && is_dedicated != 1)
+		return NULL;
+
+	/* Make sure the endpoint looks sane */
+	if ((is_dedicated && endpoint >= DDMA_DRQ_TYPE_LIMIT) ||
+	    (!is_dedicated && endpoint >= NDMA_DRQ_TYPE_LIMIT))
+		return NULL;
+
+	chan = dma_get_any_slave_channel(&priv->slave);
+	if (!chan)
+		return NULL;
+
+	/* Assign the endpoint to the vchan */
+	vchan = to_sun4i_dma_vchan(chan);
+	vchan->is_dedicated = is_dedicated;
+	vchan->endpoint = endpoint;
+
+	return chan;
+}
+
+static enum dma_status sun4i_dma_tx_status(struct dma_chan *chan,
+					   dma_cookie_t cookie,
+					   struct dma_tx_state *state)
+{
+	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
+	struct sun4i_dma_pchan *pchan = vchan->pchan;
+	struct sun4i_dma_contract *contract;
+	struct sun4i_dma_promise *promise;
+	struct virt_dma_desc *vd;
+	unsigned long flags;
+	enum dma_status ret;
+	size_t bytes = 0;
+
+	ret = dma_cookie_status(chan, cookie, state);
+	if (ret == DMA_COMPLETE)
+		return ret;
+
+	spin_lock_irqsave(&vchan->vc.lock, flags);
+	vd = vchan_find_desc(&vchan->vc, cookie);
+	if (!vd)
+		goto exit;
+	contract = to_sun4i_dma_contract(vd);
+
+	list_for_each_entry(promise, &contract->demands, list)
+		bytes += promise->len;
+
+	/*
+	 * The hardware is configured to return the remaining byte
+	 * quantity. If possible, replace the first listed element's
+	 * full size with the actual remaining amount
+	 */
+	promise = list_first_entry_or_null(&contract->demands,
+					   struct sun4i_dma_promise, list);
+	if (promise && pchan) {
+		bytes -= promise->len;
+		if (pchan->is_dedicated)
+			bytes += readl(pchan->base + DDMA_BYTE_COUNT_REG);
+		else
+			bytes += readl(pchan->base + NDMA_BYTE_COUNT_REG);
+	}
+
+exit:
+
+	dma_set_residue(state, bytes);
+	spin_unlock_irqrestore(&vchan->vc.lock, flags);
+
+	return ret;
+}
+
+static void sun4i_dma_issue_pending(struct dma_chan *chan)
+{
+	struct sun4i_dma_dev *priv = to_sun4i_dma_dev(chan->device);
+	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
+	unsigned long flags;
+
+	spin_lock_irqsave(&vchan->vc.lock, flags);
+
+	/*
+	 * If there are pending transactions for this vchan, push one of
+	 * them into the engine to get the ball rolling.
+	 */
+	if (vchan_issue_pending(&vchan->vc))
+		execute_vchan_pending(priv, vchan);
+
+	spin_unlock_irqrestore(&vchan->vc.lock, flags);
+}
+
+static irqreturn_t sun4i_dma_interrupt(int irq, void *dev_id)
+{
+	struct sun4i_dma_dev *priv = dev_id;
+	struct sun4i_dma_pchan *pchans = priv->pchans, *pchan;
+	struct sun4i_dma_vchan *vchan;
+	struct sun4i_dma_contract *contract;
+	struct sun4i_dma_promise *promise;
+	unsigned long pendirq, irqs, disableirqs = 0;
+	int bit, ret = IRQ_HANDLED;
+
+	pendirq = readl_relaxed(priv->base + DMA_IRQ_PENDING_STATUS_REG);
+
+	for_each_set_bit(bit, &pendirq, 32) {
+		pchan = &pchans[bit >> 1];
+		vchan = pchan->vchan;
+		contract = vchan->contract;
+
+		/*
+		 * Disable the IRQ and free the pchan if it's an end
+		 * interrupt (odd bit)
+		 */
+		if (bit & 1) {
+			spin_lock(&vchan->vc.lock);
+
+			/*
+			 * Move the promise into the completed list now that
+			 * we're done with it
+			 */
+			list_del(&vchan->processing->list);
+			list_add_tail(&vchan->processing->list,
+				      &contract->completed_demands);
+
+			/*
+			 * Cyclic DMA transfers are special:
+			 * - There's always something we can dispatch
+			 * - We need to run the callback
+			 * - Latency is very important, as this is used by audio
+			 * We therefore just cycle through the list and dispatch
+			 * whatever we have here, reusing the pchan. There's
+			 * no need to run the thread after this.
+			 *
+			 * For non-cyclic transfers we need to run the thread,
+			 * so it can program some more work, or notify
+			 * the client that the transfer has been completed.
+			 */
+			if (contract->is_cyclic) {
+				promise = get_next_cyclic_promise(contract);
+				configure_pchan(pchan, promise);
+				vchan->processing = promise;
+				vchan_cyclic_callback(&contract->vd);
+			} else {
+				ret = IRQ_WAKE_THREAD;
+				vchan->processing = NULL;
+				vchan->pchan = NULL;
+
+				disableirqs |= BIT(bit);
+				release_pchan(priv, pchan);
+			}
+
+			spin_unlock(&vchan->vc.lock);
+		} else {
+			/* Half done interrupt */
+			if (contract->is_cyclic)
+				vchan_cyclic_callback(&contract->vd);
+			else
+				disableirqs |= BIT(bit);
+		}
+	}
+
+	/* Disable the IRQs for events we handled */
+	spin_lock(&priv->lock);
+	irqs = readl_relaxed(priv->base + DMA_IRQ_ENABLE_REG);
+	writel_relaxed(irqs & ~disableirqs, priv->base + DMA_IRQ_ENABLE_REG);
+	spin_unlock(&priv->lock);
+
+	/* Writing 1 to the pending field will clear the pending interrupt */
+	writel_relaxed(pendirq, priv->base + DMA_IRQ_PENDING_STATUS_REG);
+
+	return ret;
+}
+
+static irqreturn_t sun4i_dma_submit_work(int irq, void *dev_id)
+{
+	struct sun4i_dma_dev *priv = dev_id;
+	struct sun4i_dma_vchan *vchan;
+	unsigned long flags;
+	int i;
+
+	for (i = 0; i < DMA_NR_MAX_VCHANS; i++) {
+		vchan = &priv->vchans[i];
+		spin_lock_irqsave(&vchan->vc.lock, flags);
+		execute_vchan_pending(priv, vchan);
+		spin_unlock_irqrestore(&vchan->vc.lock, flags);
+	}
+
+	return IRQ_HANDLED;
+}
+
+#define SUN4I_DMA_BUSWIDTHS \
+        BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
+        BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
+        BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
+        BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
+
+static int sun4i_dma_device_slave_caps(struct dma_chan *dchan,
+				       struct dma_slave_caps *caps)
+{
+	caps->src_addr_widths = SUN4I_DMA_BUSWIDTHS;
+	caps->dstn_addr_widths = SUN4I_DMA_BUSWIDTHS;
+	caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
+	caps->cmd_pause = false;
+	caps->cmd_terminate = true;
+	caps->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
+
+	return 0;
+}
+
+static int sun4i_dma_probe(struct platform_device *pdev)
+{
+	struct sun4i_dma_dev *priv;
+	struct resource *res;
+	int i, j, ret;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	priv->irq = platform_get_irq(pdev, 0);
+	if (priv->irq < 0) {
+		dev_err(&pdev->dev, "Cannot claim IRQ\n");
+		return priv->irq;
+	}
+
+	priv->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(&pdev->dev, "No clock specified\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	platform_set_drvdata(pdev, priv);
+	spin_lock_init(&priv->lock);
+
+	dma_cap_zero(priv->slave.cap_mask);
+	dma_cap_set(DMA_PRIVATE, priv->slave.cap_mask);
+	dma_cap_set(DMA_MEMCPY, priv->slave.cap_mask);
+	dma_cap_set(DMA_CYCLIC, priv->slave.cap_mask);
+	dma_cap_set(DMA_SLAVE, priv->slave.cap_mask);
+
+	INIT_LIST_HEAD(&priv->slave.channels);
+	priv->slave.device_alloc_chan_resources	= sun4i_dma_alloc_chan_resources;
+	priv->slave.device_free_chan_resources	= sun4i_dma_free_chan_resources;
+	priv->slave.device_tx_status		= sun4i_dma_tx_status;
+	priv->slave.device_issue_pending	= sun4i_dma_issue_pending;
+	priv->slave.device_prep_slave_sg	= sun4i_dma_prep_slave_sg;
+	priv->slave.device_prep_dma_memcpy	= sun4i_dma_prep_dma_memcpy;
+	priv->slave.device_prep_dma_cyclic	= sun4i_dma_prep_dma_cyclic;
+	priv->slave.device_control		= sun4i_dma_control;
+	priv->slave.device_slave_caps 		= sun4i_dma_device_slave_caps;
+	priv->slave.chancnt			= DDMA_NR_MAX_VCHANS;
+	priv->slave.copy_align			= DMA_SLAVE_BUSWIDTH_4_BYTES;
+
+	priv->slave.dev = &pdev->dev;
+
+	priv->pchans = devm_kcalloc(&pdev->dev, DMA_NR_MAX_CHANNELS,
+				    sizeof(struct sun4i_dma_pchan), GFP_KERNEL);
+	priv->vchans = devm_kcalloc(&pdev->dev, DMA_NR_MAX_VCHANS,
+				    sizeof(struct sun4i_dma_vchan), GFP_KERNEL);
+	if (!priv->vchans || !priv->pchans)
+		return -ENOMEM;
+
+	/*
+	 * [0..NDMA_NR_MAX_CHANNELS) are normal pchans, and
+	 * [NDMA_NR_MAX_CHANNELS..DMA_NR_MAX_CHANNELS) are dedicated ones
+	 */
+	for (i = 0; i < NDMA_NR_MAX_CHANNELS; i++)
+		priv->pchans[i].base = priv->base + NDMA_CHANNEL_REG_BASE(i);
+
+	for (j = 0; i < DMA_NR_MAX_CHANNELS; i++, j++) {
+		priv->pchans[i].base = priv->base + DDMA_CHANNEL_REG_BASE(j);
+		priv->pchans[i].is_dedicated = 1;
+	}
+
+	for (i = 0; i < DMA_NR_MAX_VCHANS; i++) {
+		struct sun4i_dma_vchan *vchan = &priv->vchans[i];
+
+		spin_lock_init(&vchan->vc.lock);
+		vchan->vc.desc_free = sun4i_dma_free_contract;
+		vchan_init(&vchan->vc, &priv->slave);
+	}
+
+	ret = clk_prepare_enable(priv->clk);
+	if (ret) {
+		dev_err(&pdev->dev, "Couldn't enable the clock\n");
+		return ret;
+	}
+
+	ret = devm_request_threaded_irq(&pdev->dev, priv->irq,
+					sun4i_dma_interrupt,
+					sun4i_dma_submit_work,
+					0, dev_name(&pdev->dev), priv);
+	if (ret) {
+		dev_err(&pdev->dev, "Cannot request IRQ\n");
+		goto err_clk_disable;
+	}
+
+	ret = dma_async_device_register(&priv->slave);
+	if (ret) {
+		dev_warn(&pdev->dev, "Failed to register DMA engine device\n");
+		goto err_clk_disable;
+	}
+
+	ret = of_dma_controller_register(pdev->dev.of_node, sun4i_dma_of_xlate,
+					 priv);
+	if (ret) {
+		dev_err(&pdev->dev, "of_dma_controller_register failed\n");
+		goto err_dma_unregister;
+	}
+
+	dev_dbg(&pdev->dev, "Successfully probed SUN4I_DMA\n");
+
+	return 0;
+
+err_dma_unregister:
+	dma_async_device_unregister(&priv->slave);
+err_clk_disable:
+	clk_disable_unprepare(priv->clk);
+	return ret;
+}
+
+static int sun4i_dma_remove(struct platform_device *pdev)
+{
+	struct sun4i_dma_dev *priv = platform_get_drvdata(pdev);
+
+	/* Disable IRQ so no more work is scheduled */
+	disable_irq(priv->irq);
+
+	of_dma_controller_free(pdev->dev.of_node);
+	dma_async_device_unregister(&priv->slave);
+
+	clk_disable_unprepare(priv->clk);
+
+	return 0;
+}
+
+static struct of_device_id sun4i_dma_match[] = {
+	{ .compatible = "allwinner,sun4i-a10-dma" },
+	{ /* sentinel */ },
+};
+
+static struct platform_driver sun4i_dma_driver = {
+	.probe	= sun4i_dma_probe,
+	.remove	= sun4i_dma_remove,
+	.driver	= {
+		.name		= "sun4i-dma",
+		.of_match_table	= sun4i_dma_match,
+	},
+};
+
+module_platform_driver(sun4i_dma_driver);
+
+MODULE_DESCRIPTION("Allwinner A10 Dedicated DMA Controller Driver");
+MODULE_AUTHOR("Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>");
+MODULE_LICENSE("GPL");
-- 
2.0.4
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Re: [PATCH v3 1/8] dma: sun4i: Add support for the DMA engine on sun[457]i SoCs

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 3838 bytes --]

Hi,

Overall it looks very nice, thanks.

On Mon, Aug 04, 2014 at 05:09:55PM -0300, Emilio López wrote:
> +static struct sun4i_dma_pchan *find_and_use_pchan(struct sun4i_dma_dev *priv,
> +                                                 struct sun4i_dma_vchan *vchan)
> +{
> +       struct sun4i_dma_pchan *pchan = NULL, *pchans = priv->pchans;
> +       unsigned long flags;
> +       int i, max;
> +
> +       /*
> +        * pchans 0-NDMA_NR_MAX_CHANNELS are normal, and
> +        * NDMA_NR_MAX_CHANNELS+ are dedicated ones
> +        */
> +       if (vchan->is_dedicated) {
> +               i = NDMA_NR_MAX_CHANNELS;
> +               max = DMA_NR_MAX_CHANNELS;
> +       } else {
> +               i = 0;
> +               max = NDMA_NR_MAX_CHANNELS;
> +       }
> +
> +       spin_lock_irqsave(&priv->lock, flags);
> +       for_each_clear_bit_from(i, &priv->pchans_used, max) {
> +               pchan = &pchans[i];
> +               pchan->vchan = vchan;
> +               set_bit(i, priv->pchans_used);
> +               break;

ffz instead?

> +static int execute_vchan_pending(struct sun4i_dma_dev *priv,
> +				 struct sun4i_dma_vchan *vchan)
> +{
> +	struct sun4i_dma_promise *promise = NULL;
> +	struct sun4i_dma_contract *contract = NULL;
> +	struct sun4i_dma_pchan *pchan;
> +	struct virt_dma_desc *vd;
> +	int ret;
> +
> +	lockdep_assert_held(&vchan->vc.lock);

So this has to be called with a lock taken?

You should mention that somewhere.
Usually, such fonctions are also prefixed by "__"

> +/**
> + * Generate a promise, to be used in a normal DMA contract.
> + *
> + * A NDMA promise contains all the information required to program the
> + * normal part of the DMA Engine and get data copied. A non-executed
> + * promise will live in the demands list on a contract. Once it has been
> + * completed, it will be moved to the completed demands list for later freeing.
> + * All linked promises will be freed when the corresponding contract is freed
> + */
> +static struct sun4i_dma_promise *
> +generate_ndma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest,
> +		      size_t len, struct dma_slave_config *sconfig)
> +{
> +	struct sun4i_dma_promise *promise;
> +	int ret;
> +
> +	promise = kzalloc(sizeof(*promise), GFP_NOWAIT);
> +	if (!promise)
> +		return NULL;
> +
> +	promise->src = src;
> +	promise->dst = dest;
> +	promise->len = len;
> +	promise->cfg = NDMA_CFG_LOADING | NDMA_CFG_BYTE_COUNT_MODE_REMAIN;
> +
> +	/* Use sensible default values if client is using undefined ones */
> +	if (sconfig->src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
> +		sconfig->src_addr_width = sconfig->dst_addr_width;
> +	if (sconfig->dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
> +		sconfig->dst_addr_width = sconfig->src_addr_width;
> +	if (sconfig->src_maxburst == 0)
> +		sconfig->src_maxburst = sconfig->dst_maxburst;
> +	if (sconfig->dst_maxburst == 0)
> +		sconfig->dst_maxburst = sconfig->src_maxburst;

I'm not sure what's the default policy on that. Vinod?

> +static irqreturn_t sun4i_dma_submit_work(int irq, void *dev_id)
> +{
> +	struct sun4i_dma_dev *priv = dev_id;
> +	struct sun4i_dma_vchan *vchan;
> +	unsigned long flags;
> +	int i;
> +
> +	for (i = 0; i < DMA_NR_MAX_VCHANS; i++) {
> +		vchan = &priv->vchans[i];
> +		spin_lock_irqsave(&vchan->vc.lock, flags);
> +		execute_vchan_pending(priv, vchan);
> +		spin_unlock_irqrestore(&vchan->vc.lock, flags);
> +	}
> +
> +	return IRQ_HANDLED;
> +}

Judging from Russell's comment here, that should be in the interrupt
handler

http://lists.infradead.org/pipermail/linux-arm-kernel/2014-August/277737.html

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[-- Attachment #2: Digital signature --]
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Re: [PATCH v3 1/8] dma: sun4i: Add support for the DMA engine on sun[457]i SoCs

[Emilio López]

Hi,

El 05/08/14 a las 17:00, Maxime Ripard escibió:
> Hi,
>
> Overall it looks very nice, thanks.
>
> On Mon, Aug 04, 2014 at 05:09:55PM -0300, Emilio López wrote:
>> +static struct sun4i_dma_pchan *find_and_use_pchan(struct sun4i_dma_dev *priv,
>> +                                                 struct sun4i_dma_vchan *vchan)
>> +{
>> +       struct sun4i_dma_pchan *pchan = NULL, *pchans = priv->pchans;
>> +       unsigned long flags;
>> +       int i, max;
>> +
>> +       /*
>> +        * pchans 0-NDMA_NR_MAX_CHANNELS are normal, and
>> +        * NDMA_NR_MAX_CHANNELS+ are dedicated ones
>> +        */
>> +       if (vchan->is_dedicated) {
>> +               i = NDMA_NR_MAX_CHANNELS;
>> +               max = DMA_NR_MAX_CHANNELS;
>> +       } else {
>> +               i = 0;
>> +               max = NDMA_NR_MAX_CHANNELS;
>> +       }
>> +
>> +       spin_lock_irqsave(&priv->lock, flags);
>> +       for_each_clear_bit_from(i, &priv->pchans_used, max) {
>> +               pchan = &pchans[i];
>> +               pchan->vchan = vchan;
>> +               set_bit(i, priv->pchans_used);
>> +               break;
>
> ffz instead?

I think it'd look way more messy with ffz, as it only works on unsigned 
longs and it's undefined on the all-1s case.

We could have something like this, but I don't see much point in what's 
basically expanding the macro

	spin_lock_irqsave(&priv->lock, flags);
	i = find_next_zero_bit(&priv->pchans_used, max, i);
	if (i < max) {
		pchan = &pchans[i];
		pchan->vchan = vchan;
		set_bit(i, priv->pchans_used);
	}
	spin_unlock_irqrestore(&priv->lock, flags);

>> +static int execute_vchan_pending(struct sun4i_dma_dev *priv,
>> +				 struct sun4i_dma_vchan *vchan)
>> +{
>> +	struct sun4i_dma_promise *promise = NULL;
>> +	struct sun4i_dma_contract *contract = NULL;
>> +	struct sun4i_dma_pchan *pchan;
>> +	struct virt_dma_desc *vd;
>> +	int ret;
>> +
>> +	lockdep_assert_held(&vchan->vc.lock);
>
> So this has to be called with a lock taken?
>
> You should mention that somewhere.
> Usually, such fonctions are also prefixed by "__"

Ok, I added a comment and the prefix now.

>> +/**
>> + * Generate a promise, to be used in a normal DMA contract.
>> + *
>> + * A NDMA promise contains all the information required to program the
>> + * normal part of the DMA Engine and get data copied. A non-executed
>> + * promise will live in the demands list on a contract. Once it has been
>> + * completed, it will be moved to the completed demands list for later freeing.
>> + * All linked promises will be freed when the corresponding contract is freed
>> + */
>> +static struct sun4i_dma_promise *
>> +generate_ndma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest,
>> +		      size_t len, struct dma_slave_config *sconfig)
>> +{
>> +	struct sun4i_dma_promise *promise;
>> +	int ret;
>> +
>> +	promise = kzalloc(sizeof(*promise), GFP_NOWAIT);
>> +	if (!promise)
>> +		return NULL;
>> +
>> +	promise->src = src;
>> +	promise->dst = dest;
>> +	promise->len = len;
>> +	promise->cfg = NDMA_CFG_LOADING | NDMA_CFG_BYTE_COUNT_MODE_REMAIN;
>> +
>> +	/* Use sensible default values if client is using undefined ones */
>> +	if (sconfig->src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
>> +		sconfig->src_addr_width = sconfig->dst_addr_width;
>> +	if (sconfig->dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
>> +		sconfig->dst_addr_width = sconfig->src_addr_width;
>> +	if (sconfig->src_maxburst == 0)
>> +		sconfig->src_maxburst = sconfig->dst_maxburst;
>> +	if (sconfig->dst_maxburst == 0)
>> +		sconfig->dst_maxburst = sconfig->src_maxburst;
>
> I'm not sure what's the default policy on that. Vinod?
>
>> +static irqreturn_t sun4i_dma_submit_work(int irq, void *dev_id)
>> +{
>> +	struct sun4i_dma_dev *priv = dev_id;
>> +	struct sun4i_dma_vchan *vchan;
>> +	unsigned long flags;
>> +	int i;
>> +
>> +	for (i = 0; i < DMA_NR_MAX_VCHANS; i++) {
>> +		vchan = &priv->vchans[i];
>> +		spin_lock_irqsave(&vchan->vc.lock, flags);
>> +		execute_vchan_pending(priv, vchan);
>> +		spin_unlock_irqrestore(&vchan->vc.lock, flags);
>> +	}
>> +
>> +	return IRQ_HANDLED;
>> +}
>
> Judging from Russell's comment here, that should be in the interrupt
> handler
>
> http://lists.infradead.org/pipermail/linux-arm-kernel/2014-August/277737.html

Wouldn't that make the interrupt handler quite big time wise? I was 
under the impression they should remain as short as possible. LDD3 says 
"The programmer should be careful to write a routine that executes in a 
minimum amount of time (...)" on chapter 10

I did try something mid-way a bit ago; I added code to see if we could 
issue the next DMA operation from the current set, but it was just extra 
complexity for a noop in performance, as they're sets of one on all 
cases I tried.

It's worth noting that the very latency sensitive DMA users we will have 
(ie, audio) are already completely managed in the IRQ handler thanks to 
the less flexible concept of cyclic transfers.

Cheers,

Emilio
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Re: [PATCH v3 1/8] dma: sun4i: Add support for the DMA engine on sun[457]i SoCs

[jonsmirl-Re5JQEeQqe8AvxtiuMwx3w]

On Thu, Aug 7, 2014 at 3:37 PM, Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org> wrote:
> Hi,
>
> El 05/08/14 a las 17:00, Maxime Ripard escibió:
>
>> Hi,
>>
>> Overall it looks very nice, thanks.
>>
>> On Mon, Aug 04, 2014 at 05:09:55PM -0300, Emilio López wrote:
>>>
>>> +static struct sun4i_dma_pchan *find_and_use_pchan(struct sun4i_dma_dev
>>> *priv,
>>> +                                                 struct sun4i_dma_vchan
>>> *vchan)
>>> +{
>>> +       struct sun4i_dma_pchan *pchan = NULL, *pchans = priv->pchans;
>>> +       unsigned long flags;
>>> +       int i, max;
>>> +
>>> +       /*
>>> +        * pchans 0-NDMA_NR_MAX_CHANNELS are normal, and
>>> +        * NDMA_NR_MAX_CHANNELS+ are dedicated ones
>>> +        */
>>> +       if (vchan->is_dedicated) {
>>> +               i = NDMA_NR_MAX_CHANNELS;
>>> +               max = DMA_NR_MAX_CHANNELS;
>>> +       } else {
>>> +               i = 0;
>>> +               max = NDMA_NR_MAX_CHANNELS;
>>> +       }
>>> +
>>> +       spin_lock_irqsave(&priv->lock, flags);
>>> +       for_each_clear_bit_from(i, &priv->pchans_used, max) {
>>> +               pchan = &pchans[i];
>>> +               pchan->vchan = vchan;
>>> +               set_bit(i, priv->pchans_used);
>>> +               break;
>>
>>
>> ffz instead?
>
>
> I think it'd look way more messy with ffz, as it only works on unsigned
> longs and it's undefined on the all-1s case.
>
> We could have something like this, but I don't see much point in what's
> basically expanding the macro
>
>         spin_lock_irqsave(&priv->lock, flags);
>         i = find_next_zero_bit(&priv->pchans_used, max, i);
>         if (i < max) {
>                 pchan = &pchans[i];
>                 pchan->vchan = vchan;
>                 set_bit(i, priv->pchans_used);
>         }
>         spin_unlock_irqrestore(&priv->lock, flags);
>
>
>>> +static int execute_vchan_pending(struct sun4i_dma_dev *priv,
>>> +                                struct sun4i_dma_vchan *vchan)
>>> +{
>>> +       struct sun4i_dma_promise *promise = NULL;
>>> +       struct sun4i_dma_contract *contract = NULL;
>>> +       struct sun4i_dma_pchan *pchan;
>>> +       struct virt_dma_desc *vd;
>>> +       int ret;
>>> +
>>> +       lockdep_assert_held(&vchan->vc.lock);
>>
>>
>> So this has to be called with a lock taken?
>>
>> You should mention that somewhere.
>> Usually, such fonctions are also prefixed by "__"
>
>
> Ok, I added a comment and the prefix now.
>
>
>>> +/**
>>> + * Generate a promise, to be used in a normal DMA contract.
>>> + *
>>> + * A NDMA promise contains all the information required to program the
>>> + * normal part of the DMA Engine and get data copied. A non-executed
>>> + * promise will live in the demands list on a contract. Once it has been
>>> + * completed, it will be moved to the completed demands list for later
>>> freeing.
>>> + * All linked promises will be freed when the corresponding contract is
>>> freed
>>> + */
>>> +static struct sun4i_dma_promise *
>>> +generate_ndma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t
>>> dest,
>>> +                     size_t len, struct dma_slave_config *sconfig)
>>> +{
>>> +       struct sun4i_dma_promise *promise;
>>> +       int ret;
>>> +
>>> +       promise = kzalloc(sizeof(*promise), GFP_NOWAIT);
>>> +       if (!promise)
>>> +               return NULL;
>>> +
>>> +       promise->src = src;
>>> +       promise->dst = dest;
>>> +       promise->len = len;
>>> +       promise->cfg = NDMA_CFG_LOADING |
>>> NDMA_CFG_BYTE_COUNT_MODE_REMAIN;
>>> +
>>> +       /* Use sensible default values if client is using undefined ones
>>> */
>>> +       if (sconfig->src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
>>> +               sconfig->src_addr_width = sconfig->dst_addr_width;
>>> +       if (sconfig->dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
>>> +               sconfig->dst_addr_width = sconfig->src_addr_width;
>>> +       if (sconfig->src_maxburst == 0)
>>> +               sconfig->src_maxburst = sconfig->dst_maxburst;
>>> +       if (sconfig->dst_maxburst == 0)
>>> +               sconfig->dst_maxburst = sconfig->src_maxburst;
>>
>>
>> I'm not sure what's the default policy on that. Vinod?
>>
>>> +static irqreturn_t sun4i_dma_submit_work(int irq, void *dev_id)
>>> +{
>>> +       struct sun4i_dma_dev *priv = dev_id;
>>> +       struct sun4i_dma_vchan *vchan;
>>> +       unsigned long flags;
>>> +       int i;
>>> +
>>> +       for (i = 0; i < DMA_NR_MAX_VCHANS; i++) {
>>> +               vchan = &priv->vchans[i];
>>> +               spin_lock_irqsave(&vchan->vc.lock, flags);
>>> +               execute_vchan_pending(priv, vchan);
>>> +               spin_unlock_irqrestore(&vchan->vc.lock, flags);
>>> +       }
>>> +
>>> +       return IRQ_HANDLED;
>>> +}
>>
>>
>> Judging from Russell's comment here, that should be in the interrupt
>> handler
>>
>>
>> http://lists.infradead.org/pipermail/linux-arm-kernel/2014-August/277737.html
>
>
> Wouldn't that make the interrupt handler quite big time wise? I was under
> the impression they should remain as short as possible. LDD3 says "The
> programmer should be careful to write a routine that executes in a minimum
> amount of time (...)" on chapter 10
>
> I did try something mid-way a bit ago; I added code to see if we could issue
> the next DMA operation from the current set, but it was just extra
> complexity for a noop in performance, as they're sets of one on all cases I
> tried.
>
> It's worth noting that the very latency sensitive DMA users we will have
> (ie, audio) are already completely managed in the IRQ handler thanks to the
> less flexible concept of cyclic transfers.

Other things are latency sensitive like ADC inputs. Plus adding
latency lowers the throughput of SPI and whoever else is using the
channels.

Running that code is probably just a few microseconds, not enough to
mess up overall system latency. Things that mess up system latency are
in the millisecond range.

Another thing I do in my IRQ handlers is re-read the interrupt status
register right before returning.  Then loop if any new IRQs have
asserted.   The network drivers all do this, they call it IRQ
mitigation.  Consider multiple Gbe interfaces getting hit by billions
of tiny packets. But doing IRQ mitigation you can eliminate millions
of pointless interrupts.


>
> Cheers,
>
> Emilio
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



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Re: [PATCH v3 1/8] dma: sun4i: Add support for the DMA engine on sun[457]i SoCs

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 4034 bytes --]

On Thu, Aug 07, 2014 at 04:37:16PM -0300, Emilio López wrote:
> Hi,
> 
> El 05/08/14 a las 17:00, Maxime Ripard escibió:
> >Hi,
> >
> >Overall it looks very nice, thanks.
> >
> >On Mon, Aug 04, 2014 at 05:09:55PM -0300, Emilio López wrote:
> >>+static struct sun4i_dma_pchan *find_and_use_pchan(struct sun4i_dma_dev *priv,
> >>+                                                 struct sun4i_dma_vchan *vchan)
> >>+{
> >>+       struct sun4i_dma_pchan *pchan = NULL, *pchans = priv->pchans;
> >>+       unsigned long flags;
> >>+       int i, max;
> >>+
> >>+       /*
> >>+        * pchans 0-NDMA_NR_MAX_CHANNELS are normal, and
> >>+        * NDMA_NR_MAX_CHANNELS+ are dedicated ones
> >>+        */
> >>+       if (vchan->is_dedicated) {
> >>+               i = NDMA_NR_MAX_CHANNELS;
> >>+               max = DMA_NR_MAX_CHANNELS;
> >>+       } else {
> >>+               i = 0;
> >>+               max = NDMA_NR_MAX_CHANNELS;
> >>+       }
> >>+
> >>+       spin_lock_irqsave(&priv->lock, flags);
> >>+       for_each_clear_bit_from(i, &priv->pchans_used, max) {
> >>+               pchan = &pchans[i];
> >>+               pchan->vchan = vchan;
> >>+               set_bit(i, priv->pchans_used);
> >>+               break;
> >
> >ffz instead?
> 
> I think it'd look way more messy with ffz, as it only works on
> unsigned longs and it's undefined on the all-1s case.
> 
> We could have something like this, but I don't see much point in
> what's basically expanding the macro
> 
> 	spin_lock_irqsave(&priv->lock, flags);
> 	i = find_next_zero_bit(&priv->pchans_used, max, i);
> 	if (i < max) {
> 		pchan = &pchans[i];
> 		pchan->vchan = vchan;
> 		set_bit(i, priv->pchans_used);
> 	}
> 	spin_unlock_irqrestore(&priv->lock, flags);

What about 

spin_lock_irqsave(&priv->lock, flags);
i = ffz(&priv->pchans_used);
if (!i)
   return NULL;

pchan = &pchans[i];
pchan->vchan = vchan;
set_bit(i, priv->pchans_used);

spin_unlock_irqrestore(&priv->lock, flags);

It looks quite clean to me.

> >>+static irqreturn_t sun4i_dma_submit_work(int irq, void *dev_id)
> >>+{
> >>+	struct sun4i_dma_dev *priv = dev_id;
> >>+	struct sun4i_dma_vchan *vchan;
> >>+	unsigned long flags;
> >>+	int i;
> >>+
> >>+	for (i = 0; i < DMA_NR_MAX_VCHANS; i++) {
> >>+		vchan = &priv->vchans[i];
> >>+		spin_lock_irqsave(&vchan->vc.lock, flags);
> >>+		execute_vchan_pending(priv, vchan);
> >>+		spin_unlock_irqrestore(&vchan->vc.lock, flags);
> >>+	}
> >>+
> >>+	return IRQ_HANDLED;
> >>+}
> >
> >Judging from Russell's comment here, that should be in the interrupt
> >handler
> >
> >http://lists.infradead.org/pipermail/linux-arm-kernel/2014-August/277737.html
> 
> Wouldn't that make the interrupt handler quite big time wise? I was
> under the impression they should remain as short as possible. LDD3
> says "The programmer should be careful to write a routine that
> executes in a minimum amount of time (...)" on chapter 10

Yeah, but if that involves delaying a lot a task that should have been
performed asap, it would make sense.

Plus, besides the loop in the contract's demands,
execute_vchan_pending is actually rather small. Did you timed it to
have such concerns?

> I did try something mid-way a bit ago; I added code to see if we
> could issue the next DMA operation from the current set, but it was
> just extra complexity for a noop in performance, as they're sets of
> one on all cases I tried.
> 
> It's worth noting that the very latency sensitive DMA users we will
> have (ie, audio) are already completely managed in the IRQ handler
> thanks to the less flexible concept of cyclic transfers.

It's not just a matter of latency, but also of throughput. If you wait
for the tasklet softirq to be executed to schedule a new vchan, you
aren't going to do anything during that time, while you could have.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

Re: [PATCH v3 1/8] dma: sun4i: Add support for the DMA engine on sun[457]i SoCs

[jonsmirl-Re5JQEeQqe8AvxtiuMwx3w]

On Mon, Aug 11, 2014 at 7:40 AM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> On Thu, Aug 07, 2014 at 04:37:16PM -0300, Emilio López wrote:
>> Hi,
>>
>> El 05/08/14 a las 17:00, Maxime Ripard escibió:
>> >Hi,
>> >
>> >Overall it looks very nice, thanks.
>> >
>> >On Mon, Aug 04, 2014 at 05:09:55PM -0300, Emilio López wrote:
>> >>+static struct sun4i_dma_pchan *find_and_use_pchan(struct sun4i_dma_dev *priv,
>> >>+                                                 struct sun4i_dma_vchan *vchan)
>> >>+{
>> >>+       struct sun4i_dma_pchan *pchan = NULL, *pchans = priv->pchans;
>> >>+       unsigned long flags;
>> >>+       int i, max;
>> >>+
>> >>+       /*
>> >>+        * pchans 0-NDMA_NR_MAX_CHANNELS are normal, and
>> >>+        * NDMA_NR_MAX_CHANNELS+ are dedicated ones
>> >>+        */
>> >>+       if (vchan->is_dedicated) {
>> >>+               i = NDMA_NR_MAX_CHANNELS;
>> >>+               max = DMA_NR_MAX_CHANNELS;
>> >>+       } else {
>> >>+               i = 0;
>> >>+               max = NDMA_NR_MAX_CHANNELS;
>> >>+       }
>> >>+
>> >>+       spin_lock_irqsave(&priv->lock, flags);
>> >>+       for_each_clear_bit_from(i, &priv->pchans_used, max) {
>> >>+               pchan = &pchans[i];
>> >>+               pchan->vchan = vchan;
>> >>+               set_bit(i, priv->pchans_used);
>> >>+               break;
>> >
>> >ffz instead?
>>
>> I think it'd look way more messy with ffz, as it only works on
>> unsigned longs and it's undefined on the all-1s case.
>>
>> We could have something like this, but I don't see much point in
>> what's basically expanding the macro
>>
>>       spin_lock_irqsave(&priv->lock, flags);
>>       i = find_next_zero_bit(&priv->pchans_used, max, i);
>>       if (i < max) {
>>               pchan = &pchans[i];
>>               pchan->vchan = vchan;
>>               set_bit(i, priv->pchans_used);
>>       }
>>       spin_unlock_irqrestore(&priv->lock, flags);
>
> What about
>
> spin_lock_irqsave(&priv->lock, flags);
> i = ffz(&priv->pchans_used);
> if (!i)
>    return NULL;
>
> pchan = &pchans[i];
> pchan->vchan = vchan;
> set_bit(i, priv->pchans_used);
>
> spin_unlock_irqrestore(&priv->lock, flags);
>
> It looks quite clean to me.
>
>> >>+static irqreturn_t sun4i_dma_submit_work(int irq, void *dev_id)
>> >>+{
>> >>+   struct sun4i_dma_dev *priv = dev_id;
>> >>+   struct sun4i_dma_vchan *vchan;
>> >>+   unsigned long flags;
>> >>+   int i;
>> >>+
>> >>+   for (i = 0; i < DMA_NR_MAX_VCHANS; i++) {
>> >>+           vchan = &priv->vchans[i];
>> >>+           spin_lock_irqsave(&vchan->vc.lock, flags);
>> >>+           execute_vchan_pending(priv, vchan);
>> >>+           spin_unlock_irqrestore(&vchan->vc.lock, flags);
>> >>+   }
>> >>+
>> >>+   return IRQ_HANDLED;
>> >>+}
>> >
>> >Judging from Russell's comment here, that should be in the interrupt
>> >handler
>> >
>> >http://lists.infradead.org/pipermail/linux-arm-kernel/2014-August/277737.html
>>
>> Wouldn't that make the interrupt handler quite big time wise? I was
>> under the impression they should remain as short as possible. LDD3
>> says "The programmer should be careful to write a routine that
>> executes in a minimum amount of time (...)" on chapter 10
>
> Yeah, but if that involves delaying a lot a task that should have been
> performed asap, it would make sense.
>
> Plus, besides the loop in the contract's demands,
> execute_vchan_pending is actually rather small. Did you timed it to
> have such concerns?
>
>> I did try something mid-way a bit ago; I added code to see if we
>> could issue the next DMA operation from the current set, but it was
>> just extra complexity for a noop in performance, as they're sets of
>> one on all cases I tried.
>>
>> It's worth noting that the very latency sensitive DMA users we will
>> have (ie, audio) are already completely managed in the IRQ handler
>> thanks to the less flexible concept of cyclic transfers.
>
> It's not just a matter of latency, but also of throughput. If you wait
> for the tasklet softirq to be executed to schedule a new vchan, you
> aren't going to do anything during that time, while you could have.

This throughput issue is an important point. It can be so important
that I have worked on some CPUs that address it in hardware by having
shadow DMA registers.  You pre-load the shadow register set and then
the DMA engine can instantly go onto the next request in hardware.

For example if the transport stream (video input) hardware on this CPU
is turned on it is going to need high throughput DMA.


>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



-- 
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jonsmirl-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
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[PATCH v3 2/8] spi: sun4i: add DMA support

[Emilio López]

This patch adds support for 64 byte or bigger transfers on the
sun4i SPI controller. Said transfers will be performed via DMA.

Signed-off-by: Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
---

Changes from v2:
 * Fix commit message

Changes from v1:
 * remove 64 byte limitation on transfers
 * wrap stuff so it fits better in 80 cols

 drivers/spi/spi-sun4i.c | 155 ++++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 144 insertions(+), 11 deletions(-)

diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c
index 85204c9..e674100 100644
--- a/drivers/spi/spi-sun4i.c
+++ b/drivers/spi/spi-sun4i.c
@@ -14,6 +14,8 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/device.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/module.h>
@@ -34,6 +36,7 @@
 #define SUN4I_CTL_CPHA				BIT(2)
 #define SUN4I_CTL_CPOL				BIT(3)
 #define SUN4I_CTL_CS_ACTIVE_LOW			BIT(4)
+#define SUN4I_CTL_DMAMC_DEDICATED		BIT(5)
 #define SUN4I_CTL_LMTF				BIT(6)
 #define SUN4I_CTL_TF_RST			BIT(8)
 #define SUN4I_CTL_RF_RST			BIT(9)
@@ -51,6 +54,8 @@
 #define SUN4I_INT_STA_REG		0x10
 
 #define SUN4I_DMA_CTL_REG		0x14
+#define SUN4I_DMA_CTL_RF_READY			BIT(0)
+#define SUN4I_DMA_CTL_TF_NOT_FULL		BIT(10)
 
 #define SUN4I_WAIT_REG			0x18
 
@@ -84,6 +89,9 @@ struct sun4i_spi {
 	const u8		*tx_buf;
 	u8			*rx_buf;
 	int			len;
+
+	struct dma_chan		*rx_dma_chan;
+	struct dma_chan		*tx_dma_chan;
 };
 
 static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg)
@@ -130,6 +138,24 @@ static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
 	}
 }
 
+static bool sun4i_spi_can_dma(struct spi_master *master,
+			      struct spi_device *spi,
+			      struct spi_transfer *tfr)
+{
+	return tfr->len >= SUN4I_FIFO_DEPTH;
+}
+
+static int sun4i_spi_prepare_message(struct spi_master *master,
+				     struct spi_message *msg)
+{
+	struct sun4i_spi *sspi = spi_master_get_devdata(master);
+
+	master->dma_rx = sspi->rx_dma_chan;
+	master->dma_tx = sspi->tx_dma_chan;
+
+	return 0;
+}
+
 static void sun4i_spi_set_cs(struct spi_device *spi, bool enable)
 {
 	struct sun4i_spi *sspi = spi_master_get_devdata(spi->master);
@@ -169,15 +195,12 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
 				  struct spi_transfer *tfr)
 {
 	struct sun4i_spi *sspi = spi_master_get_devdata(master);
+	struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
 	unsigned int mclk_rate, div, timeout;
 	unsigned int tx_len = 0;
 	int ret = 0;
 	u32 reg;
 
-	/* We don't support transfer larger than the FIFO */
-	if (tfr->len > SUN4I_FIFO_DEPTH)
-		return -EINVAL;
-
 	reinit_completion(&sspi->done);
 	sspi->tx_buf = tfr->tx_buf;
 	sspi->rx_buf = tfr->rx_buf;
@@ -186,7 +209,6 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
 	/* Clear pending interrupts */
 	sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0);
 
-
 	reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
 
 	/* Reset FIFOs */
@@ -269,12 +291,63 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
 	sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
 	sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
 
-	/* Fill the TX FIFO */
-	sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
-
 	/* Enable the interrupts */
 	sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);
 
+	if (sun4i_spi_can_dma(master, spi, tfr)) {
+		dev_dbg(&sspi->master->dev, "Using DMA mode for transfer\n");
+
+		if (sspi->tx_buf) {
+			desc_tx = dmaengine_prep_slave_sg(sspi->tx_dma_chan,
+					tfr->tx_sg.sgl, tfr->tx_sg.nents,
+					DMA_TO_DEVICE,
+					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+			if (!desc_tx) {
+				dev_err(&sspi->master->dev,
+					"Couldn't prepare dma slave\n");
+				return -EIO;
+			}
+
+			dmaengine_submit(desc_tx);
+		}
+
+		if (sspi->rx_buf) {
+			desc_rx = dmaengine_prep_slave_sg(sspi->rx_dma_chan,
+					tfr->rx_sg.sgl, tfr->rx_sg.nents,
+					DMA_FROM_DEVICE,
+					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+			if (!desc_rx) {
+				dev_err(&sspi->master->dev,
+					"Couldn't prepare dma slave\n");
+				return -EIO;
+			}
+
+			dmaengine_submit(desc_rx);
+		}
+
+		/* Enable DMA requests */
+		reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
+		sun4i_spi_write(sspi, SUN4I_CTL_REG,
+				reg | SUN4I_CTL_DMAMC_DEDICATED);
+		sun4i_spi_write(sspi, SUN4I_DMA_CTL_REG,
+				SUN4I_DMA_CTL_TF_NOT_FULL |
+				SUN4I_DMA_CTL_RF_READY);
+
+		dma_async_issue_pending(sspi->rx_dma_chan);
+		dma_async_issue_pending(sspi->tx_dma_chan);
+	} else {
+		dev_dbg(&sspi->master->dev, "Using PIO mode for transfer\n");
+
+		/* Disable DMA requests */
+		reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
+		sun4i_spi_write(sspi, SUN4I_CTL_REG,
+				reg & ~SUN4I_CTL_DMAMC_DEDICATED);
+		sun4i_spi_write(sspi, SUN4I_DMA_CTL_REG, 0);
+
+		/* Fill the TX FIFO */
+		sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
+	}
+
 	/* Start the transfer */
 	reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
 	sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
@@ -286,7 +359,12 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
 		goto out;
 	}
 
-	sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
+	if (sun4i_spi_can_dma(master, spi, tfr) && desc_rx) {
+		/* The receive transfer should be the last one to finish */
+		dma_wait_for_async_tx(desc_rx);
+	} else {
+		sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
+	}
 
 out:
 	sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
@@ -351,6 +429,7 @@ static int sun4i_spi_runtime_suspend(struct device *dev)
 
 static int sun4i_spi_probe(struct platform_device *pdev)
 {
+	struct dma_slave_config dma_sconfig;
 	struct spi_master *master;
 	struct sun4i_spi *sspi;
 	struct resource	*res;
@@ -386,7 +465,10 @@ static int sun4i_spi_probe(struct platform_device *pdev)
 		goto err_free_master;
 	}
 
+	init_completion(&sspi->done);
 	sspi->master = master;
+	master->can_dma = sun4i_spi_can_dma;
+	master->prepare_message = sun4i_spi_prepare_message;
 	master->set_cs = sun4i_spi_set_cs;
 	master->transfer_one = sun4i_spi_transfer_one;
 	master->num_chipselect = 4;
@@ -409,7 +491,45 @@ static int sun4i_spi_probe(struct platform_device *pdev)
 		goto err_free_master;
 	}
 
-	init_completion(&sspi->done);
+	sspi->tx_dma_chan = dma_request_slave_channel_reason(&pdev->dev, "tx");
+	if (IS_ERR(sspi->tx_dma_chan)) {
+		dev_err(&pdev->dev, "Unable to acquire DMA channel TX\n");
+		ret = PTR_ERR(sspi->tx_dma_chan);
+		goto err_free_master;
+	}
+
+	dma_sconfig.direction = DMA_MEM_TO_DEV;
+	dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+	dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+	dma_sconfig.dst_addr = res->start + SUN4I_TXDATA_REG;
+	dma_sconfig.src_maxburst = 1;
+	dma_sconfig.dst_maxburst = 1;
+
+	ret = dmaengine_slave_config(sspi->tx_dma_chan, &dma_sconfig);
+	if (ret) {
+		dev_err(&pdev->dev, "Unable to configure TX DMA slave\n");
+		goto err_tx_dma_release;
+	}
+
+	sspi->rx_dma_chan = dma_request_slave_channel_reason(&pdev->dev, "rx");
+	if (IS_ERR(sspi->rx_dma_chan)) {
+		dev_err(&pdev->dev, "Unable to acquire DMA channel RX\n");
+		ret = PTR_ERR(sspi->rx_dma_chan);
+		goto err_tx_dma_release;
+	}
+
+	dma_sconfig.direction = DMA_DEV_TO_MEM;
+	dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+	dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+	dma_sconfig.src_addr = res->start + SUN4I_RXDATA_REG;
+	dma_sconfig.src_maxburst = 1;
+	dma_sconfig.dst_maxburst = 1;
+
+	ret = dmaengine_slave_config(sspi->rx_dma_chan, &dma_sconfig);
+	if (ret) {
+		dev_err(&pdev->dev, "Unable to configure RX DMA slave\n");
+		goto err_rx_dma_release;
+	}
 
 	/*
 	 * This wake-up/shutdown pattern is to be able to have the
@@ -418,7 +538,7 @@ static int sun4i_spi_probe(struct platform_device *pdev)
 	ret = sun4i_spi_runtime_resume(&pdev->dev);
 	if (ret) {
 		dev_err(&pdev->dev, "Couldn't resume the device\n");
-		goto err_free_master;
+		goto err_rx_dma_release;
 	}
 
 	pm_runtime_set_active(&pdev->dev);
@@ -436,6 +556,10 @@ static int sun4i_spi_probe(struct platform_device *pdev)
 err_pm_disable:
 	pm_runtime_disable(&pdev->dev);
 	sun4i_spi_runtime_suspend(&pdev->dev);
+err_rx_dma_release:
+	dma_release_channel(sspi->rx_dma_chan);
+err_tx_dma_release:
+	dma_release_channel(sspi->tx_dma_chan);
 err_free_master:
 	spi_master_put(master);
 	return ret;
@@ -443,8 +567,17 @@ err_free_master:
 
 static int sun4i_spi_remove(struct platform_device *pdev)
 {
+	struct spi_master *master = platform_get_drvdata(pdev);
+	struct sun4i_spi *sspi = spi_master_get_devdata(master);
+
+	if (pm_runtime_active(&pdev->dev))
+		sun4i_spi_runtime_suspend(&pdev->dev);
+
 	pm_runtime_disable(&pdev->dev);
 
+	dma_release_channel(sspi->rx_dma_chan);
+	dma_release_channel(sspi->tx_dma_chan);
+
 	return 0;
 }
 
-- 
2.0.4
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Re: [PATCH v3 2/8] spi: sun4i: add DMA support

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 6167 bytes --]

Hi,

On Mon, Aug 04, 2014 at 05:09:56PM -0300, Emilio López wrote:
> +	if (sun4i_spi_can_dma(master, spi, tfr)) {
> +		dev_dbg(&sspi->master->dev, "Using DMA mode for transfer\n");
> +
> +		if (sspi->tx_buf) {
> +			desc_tx = dmaengine_prep_slave_sg(sspi->tx_dma_chan,
> +					tfr->tx_sg.sgl, tfr->tx_sg.nents,
> +					DMA_TO_DEVICE,
> +					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
> +			if (!desc_tx) {
> +				dev_err(&sspi->master->dev,
> +					"Couldn't prepare dma slave\n");
> +				return -EIO;
> +			}
> +
> +			dmaengine_submit(desc_tx);
> +		}
> +
> +		if (sspi->rx_buf) {
> +			desc_rx = dmaengine_prep_slave_sg(sspi->rx_dma_chan,
> +					tfr->rx_sg.sgl, tfr->rx_sg.nents,
> +					DMA_FROM_DEVICE,
> +					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
> +			if (!desc_rx) {
> +				dev_err(&sspi->master->dev,
> +					"Couldn't prepare dma slave\n");
> +				return -EIO;
> +			}
> +
> +			dmaengine_submit(desc_rx);
> +		}
> +
> +		/* Enable DMA requests */
> +		reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
> +		sun4i_spi_write(sspi, SUN4I_CTL_REG,
> +				reg | SUN4I_CTL_DMAMC_DEDICATED);
> +		sun4i_spi_write(sspi, SUN4I_DMA_CTL_REG,
> +				SUN4I_DMA_CTL_TF_NOT_FULL |
> +				SUN4I_DMA_CTL_RF_READY);
> +
> +		dma_async_issue_pending(sspi->rx_dma_chan);
> +		dma_async_issue_pending(sspi->tx_dma_chan);

I guess the DMA levels setup and the issue pending calls could be
moved to the if statements above about wether the RX and TX buffers
are here or not.

> +	} else {
> +		dev_dbg(&sspi->master->dev, "Using PIO mode for transfer\n");
> +
> +		/* Disable DMA requests */
> +		reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
> +		sun4i_spi_write(sspi, SUN4I_CTL_REG,
> +				reg & ~SUN4I_CTL_DMAMC_DEDICATED);
> +		sun4i_spi_write(sspi, SUN4I_DMA_CTL_REG, 0);
> +
> +		/* Fill the TX FIFO */
> +		sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
> +	}
> +
>  	/* Start the transfer */
>  	reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
>  	sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
> @@ -286,7 +359,12 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
>  		goto out;
>  	}
>  
> -	sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
> +	if (sun4i_spi_can_dma(master, spi, tfr) && desc_rx) {
> +		/* The receive transfer should be the last one to finish */
> +		dma_wait_for_async_tx(desc_rx);
> +	} else {
> +		sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
> +	}
>  
>  out:
>  	sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
> @@ -351,6 +429,7 @@ static int sun4i_spi_runtime_suspend(struct device *dev)
>  
>  static int sun4i_spi_probe(struct platform_device *pdev)
>  {
> +	struct dma_slave_config dma_sconfig;
>  	struct spi_master *master;
>  	struct sun4i_spi *sspi;
>  	struct resource	*res;
> @@ -386,7 +465,10 @@ static int sun4i_spi_probe(struct platform_device *pdev)
>  		goto err_free_master;
>  	}
>  
> +	init_completion(&sspi->done);
>  	sspi->master = master;
> +	master->can_dma = sun4i_spi_can_dma;
> +	master->prepare_message = sun4i_spi_prepare_message;
>  	master->set_cs = sun4i_spi_set_cs;
>  	master->transfer_one = sun4i_spi_transfer_one;
>  	master->num_chipselect = 4;
> @@ -409,7 +491,45 @@ static int sun4i_spi_probe(struct platform_device *pdev)
>  		goto err_free_master;
>  	}
>  
> -	init_completion(&sspi->done);
> +	sspi->tx_dma_chan = dma_request_slave_channel_reason(&pdev->dev, "tx");
> +	if (IS_ERR(sspi->tx_dma_chan)) {
> +		dev_err(&pdev->dev, "Unable to acquire DMA channel TX\n");
> +		ret = PTR_ERR(sspi->tx_dma_chan);
> +		goto err_free_master;
> +	}
> +
> +	dma_sconfig.direction = DMA_MEM_TO_DEV;
> +	dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
> +	dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
> +	dma_sconfig.dst_addr = res->start + SUN4I_TXDATA_REG;
> +	dma_sconfig.src_maxburst = 1;
> +	dma_sconfig.dst_maxburst = 1;
> +
> +	ret = dmaengine_slave_config(sspi->tx_dma_chan, &dma_sconfig);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Unable to configure TX DMA slave\n");
> +		goto err_tx_dma_release;
> +	}
> +
> +	sspi->rx_dma_chan = dma_request_slave_channel_reason(&pdev->dev, "rx");
> +	if (IS_ERR(sspi->rx_dma_chan)) {
> +		dev_err(&pdev->dev, "Unable to acquire DMA channel RX\n");
> +		ret = PTR_ERR(sspi->rx_dma_chan);
> +		goto err_tx_dma_release;
> +	}
> +
> +	dma_sconfig.direction = DMA_DEV_TO_MEM;
> +	dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
> +	dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
> +	dma_sconfig.src_addr = res->start + SUN4I_RXDATA_REG;
> +	dma_sconfig.src_maxburst = 1;
> +	dma_sconfig.dst_maxburst = 1;
> +
> +	ret = dmaengine_slave_config(sspi->rx_dma_chan, &dma_sconfig);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Unable to configure RX DMA slave\n");
> +		goto err_rx_dma_release;
> +	}
>  
>  	/*
>  	 * This wake-up/shutdown pattern is to be able to have the
> @@ -418,7 +538,7 @@ static int sun4i_spi_probe(struct platform_device *pdev)
>  	ret = sun4i_spi_runtime_resume(&pdev->dev);
>  	if (ret) {
>  		dev_err(&pdev->dev, "Couldn't resume the device\n");
> -		goto err_free_master;
> +		goto err_rx_dma_release;
>  	}
>  
>  	pm_runtime_set_active(&pdev->dev);
> @@ -436,6 +556,10 @@ static int sun4i_spi_probe(struct platform_device *pdev)
>  err_pm_disable:
>  	pm_runtime_disable(&pdev->dev);
>  	sun4i_spi_runtime_suspend(&pdev->dev);
> +err_rx_dma_release:
> +	dma_release_channel(sspi->rx_dma_chan);
> +err_tx_dma_release:
> +	dma_release_channel(sspi->tx_dma_chan);
>  err_free_master:
>  	spi_master_put(master);
>  	return ret;
> @@ -443,8 +567,17 @@ err_free_master:
>  
>  static int sun4i_spi_remove(struct platform_device *pdev)
>  {
> +	struct spi_master *master = platform_get_drvdata(pdev);
> +	struct sun4i_spi *sspi = spi_master_get_devdata(master);
> +
> +	if (pm_runtime_active(&pdev->dev))
> +		sun4i_spi_runtime_suspend(&pdev->dev);
> +

This doesn't really belong in this patch, please send a separate one.

Maxime

-- 
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[-- Attachment #2: Digital signature --]
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Re: [PATCH v3 2/8] spi: sun4i: add DMA support

[Emilio López]

Hi Maxime,

El 05/08/14 a las 17:23, Maxime Ripard escibió:
> Hi,
>
> On Mon, Aug 04, 2014 at 05:09:56PM -0300, Emilio López wrote:
>> +	if (sun4i_spi_can_dma(master, spi, tfr)) {
>> +		dev_dbg(&sspi->master->dev, "Using DMA mode for transfer\n");
>> +
>> +		if (sspi->tx_buf) {
>> +			desc_tx = dmaengine_prep_slave_sg(sspi->tx_dma_chan,
>> +					tfr->tx_sg.sgl, tfr->tx_sg.nents,
>> +					DMA_TO_DEVICE,
>> +					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
>> +			if (!desc_tx) {
>> +				dev_err(&sspi->master->dev,
>> +					"Couldn't prepare dma slave\n");
>> +				return -EIO;
>> +			}
>> +
>> +			dmaengine_submit(desc_tx);
>> +		}
>> +
>> +		if (sspi->rx_buf) {
>> +			desc_rx = dmaengine_prep_slave_sg(sspi->rx_dma_chan,
>> +					tfr->rx_sg.sgl, tfr->rx_sg.nents,
>> +					DMA_FROM_DEVICE,
>> +					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
>> +			if (!desc_rx) {
>> +				dev_err(&sspi->master->dev,
>> +					"Couldn't prepare dma slave\n");
>> +				return -EIO;
>> +			}
>> +
>> +			dmaengine_submit(desc_rx);
>> +		}
>> +
>> +		/* Enable DMA requests */
>> +		reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
>> +		sun4i_spi_write(sspi, SUN4I_CTL_REG,
>> +				reg | SUN4I_CTL_DMAMC_DEDICATED);
>> +		sun4i_spi_write(sspi, SUN4I_DMA_CTL_REG,
>> +				SUN4I_DMA_CTL_TF_NOT_FULL |
>> +				SUN4I_DMA_CTL_RF_READY);
>> +
>> +		dma_async_issue_pending(sspi->rx_dma_chan);
>> +		dma_async_issue_pending(sspi->tx_dma_chan);
>
> I guess the DMA levels setup and the issue pending calls could be
> moved to the if statements above about wether the RX and TX buffers
> are here or not.

Ok, I'll do that.

>> +	} else {
>> +		dev_dbg(&sspi->master->dev, "Using PIO mode for transfer\n");
>> +
>> +		/* Disable DMA requests */
>> +		reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
>> +		sun4i_spi_write(sspi, SUN4I_CTL_REG,
>> +				reg & ~SUN4I_CTL_DMAMC_DEDICATED);
>> +		sun4i_spi_write(sspi, SUN4I_DMA_CTL_REG, 0);
>> +
>> +		/* Fill the TX FIFO */
>> +		sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
>> +	}
>> +
>>   	/* Start the transfer */
>>   	reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
>>   	sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
>> @@ -286,7 +359,12 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
>>   		goto out;
>>   	}
>>
>> -	sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
>> +	if (sun4i_spi_can_dma(master, spi, tfr) && desc_rx) {
>> +		/* The receive transfer should be the last one to finish */
>> +		dma_wait_for_async_tx(desc_rx);
>> +	} else {
>> +		sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
>> +	}
>>
>>   out:
>>   	sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
>> @@ -351,6 +429,7 @@ static int sun4i_spi_runtime_suspend(struct device *dev)
>>
>>   static int sun4i_spi_probe(struct platform_device *pdev)
>>   {
>> +	struct dma_slave_config dma_sconfig;
>>   	struct spi_master *master;
>>   	struct sun4i_spi *sspi;
>>   	struct resource	*res;
>> @@ -386,7 +465,10 @@ static int sun4i_spi_probe(struct platform_device *pdev)
>>   		goto err_free_master;
>>   	}
>>
>> +	init_completion(&sspi->done);
>>   	sspi->master = master;
>> +	master->can_dma = sun4i_spi_can_dma;
>> +	master->prepare_message = sun4i_spi_prepare_message;
>>   	master->set_cs = sun4i_spi_set_cs;
>>   	master->transfer_one = sun4i_spi_transfer_one;
>>   	master->num_chipselect = 4;
>> @@ -409,7 +491,45 @@ static int sun4i_spi_probe(struct platform_device *pdev)
>>   		goto err_free_master;
>>   	}
>>
>> -	init_completion(&sspi->done);
>> +	sspi->tx_dma_chan = dma_request_slave_channel_reason(&pdev->dev, "tx");
>> +	if (IS_ERR(sspi->tx_dma_chan)) {
>> +		dev_err(&pdev->dev, "Unable to acquire DMA channel TX\n");
>> +		ret = PTR_ERR(sspi->tx_dma_chan);
>> +		goto err_free_master;
>> +	}
>> +
>> +	dma_sconfig.direction = DMA_MEM_TO_DEV;
>> +	dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
>> +	dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
>> +	dma_sconfig.dst_addr = res->start + SUN4I_TXDATA_REG;
>> +	dma_sconfig.src_maxburst = 1;
>> +	dma_sconfig.dst_maxburst = 1;
>> +
>> +	ret = dmaengine_slave_config(sspi->tx_dma_chan, &dma_sconfig);
>> +	if (ret) {
>> +		dev_err(&pdev->dev, "Unable to configure TX DMA slave\n");
>> +		goto err_tx_dma_release;
>> +	}
>> +
>> +	sspi->rx_dma_chan = dma_request_slave_channel_reason(&pdev->dev, "rx");
>> +	if (IS_ERR(sspi->rx_dma_chan)) {
>> +		dev_err(&pdev->dev, "Unable to acquire DMA channel RX\n");
>> +		ret = PTR_ERR(sspi->rx_dma_chan);
>> +		goto err_tx_dma_release;
>> +	}
>> +
>> +	dma_sconfig.direction = DMA_DEV_TO_MEM;
>> +	dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
>> +	dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
>> +	dma_sconfig.src_addr = res->start + SUN4I_RXDATA_REG;
>> +	dma_sconfig.src_maxburst = 1;
>> +	dma_sconfig.dst_maxburst = 1;
>> +
>> +	ret = dmaengine_slave_config(sspi->rx_dma_chan, &dma_sconfig);
>> +	if (ret) {
>> +		dev_err(&pdev->dev, "Unable to configure RX DMA slave\n");
>> +		goto err_rx_dma_release;
>> +	}
>>
>>   	/*
>>   	 * This wake-up/shutdown pattern is to be able to have the
>> @@ -418,7 +538,7 @@ static int sun4i_spi_probe(struct platform_device *pdev)
>>   	ret = sun4i_spi_runtime_resume(&pdev->dev);
>>   	if (ret) {
>>   		dev_err(&pdev->dev, "Couldn't resume the device\n");
>> -		goto err_free_master;
>> +		goto err_rx_dma_release;
>>   	}
>>
>>   	pm_runtime_set_active(&pdev->dev);
>> @@ -436,6 +556,10 @@ static int sun4i_spi_probe(struct platform_device *pdev)
>>   err_pm_disable:
>>   	pm_runtime_disable(&pdev->dev);
>>   	sun4i_spi_runtime_suspend(&pdev->dev);
>> +err_rx_dma_release:
>> +	dma_release_channel(sspi->rx_dma_chan);
>> +err_tx_dma_release:
>> +	dma_release_channel(sspi->tx_dma_chan);
>>   err_free_master:
>>   	spi_master_put(master);
>>   	return ret;
>> @@ -443,8 +567,17 @@ err_free_master:
>>
>>   static int sun4i_spi_remove(struct platform_device *pdev)
>>   {
>> +	struct spi_master *master = platform_get_drvdata(pdev);
>> +	struct sun4i_spi *sspi = spi_master_get_devdata(master);
>> +
>> +	if (pm_runtime_active(&pdev->dev))
>> +		sun4i_spi_runtime_suspend(&pdev->dev);
>> +
>
> This doesn't really belong in this patch, please send a separate one.

Sure

Thanks!

Emilio
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Re: [PATCH v3 2/8] spi: sun4i: add DMA support

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 418 bytes --]

On Mon, Aug 04, 2014 at 05:09:56PM -0300, Emilio López wrote:

> +static int sun4i_spi_prepare_message(struct spi_master *master,
> +				     struct spi_message *msg)
> +{
> +	struct sun4i_spi *sspi = spi_master_get_devdata(master);
> +
> +	master->dma_rx = sspi->rx_dma_chan;
> +	master->dma_tx = sspi->tx_dma_chan;
> +
> +	return 0;
> +}

Why is this being done per transfer rather than at probe time?

[-- Attachment #2: Digital signature --]
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[PATCH v3 3/8] ARM: sun4i: dt: Add node to represent the DMA controller

[Emilio López]

Let's add a node to represent the A10 DMA controller on the device tree.

Signed-off-by: Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
Reviewed-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---

Changes from v2:
 * Fix whitespace
 * Collect tag from Chen-Yu

 arch/arm/boot/dts/sun4i-a10.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index d96e179..5c6791a 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -339,6 +339,14 @@
 		#size-cells = <1>;
 		ranges;
 
+		dma: dma-controller@01c02000 {
+			compatible = "allwinner,sun4i-a10-dma";
+			reg = <0x01c02000 0x1000>;
+			interrupts = <27>;
+			clocks = <&ahb_gates 6>;
+			#dma-cells = <2>;
+		};
+
 		spi0: spi@01c05000 {
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c05000 0x1000>;
-- 
2.0.4
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Re: [PATCH v3 3/8] ARM: sun4i: dt: Add node to represent the DMA controller

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 463 bytes --]

On Mon, Aug 04, 2014 at 05:09:57PM -0300, Emilio López wrote:
> Let's add a node to represent the A10 DMA controller on the device tree.
> 
> Signed-off-by: Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
> Reviewed-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>

Merged, together with the next patches.

Thanks!
Maxime

-- 
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[PATCH v3 4/8] ARM: sun5i: dt: Add nodes to represent the DMA controllers

[Emilio López]

The A10S and A13 SoCs have sun4i-compatible DMA controllers. Let's add
the corresponding nodes to represent them on the device tree.

Signed-off-by: Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
Reviewed-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---

Changes from v2:
 * Fix whitespace
 * Collect tag from Chen-Yu

Note that I have only tested on A10S, if anyone with an A13 device could
test as well, that would be great! I don't expect any issues however.

 arch/arm/boot/dts/sun5i-a10s.dtsi | 8 ++++++++
 arch/arm/boot/dts/sun5i-a13.dtsi  | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index b64f705..8b5a27c 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -300,6 +300,14 @@
 		#size-cells = <1>;
 		ranges;
 
+		dma: dma-controller@01c02000 {
+			compatible = "allwinner,sun4i-a10-dma";
+			reg = <0x01c02000 0x1000>;
+			interrupts = <27>;
+			clocks = <&ahb_gates 6>;
+			#dma-cells = <2>;
+		};
+
 		spi0: spi@01c05000 {
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c05000 0x1000>;
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 3b2a94c..139f4ac 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -298,6 +298,14 @@
 		#size-cells = <1>;
 		ranges;
 
+		dma: dma-controller@01c02000 {
+			compatible = "allwinner,sun4i-a10-dma";
+			reg = <0x01c02000 0x1000>;
+			interrupts = <27>;
+			clocks = <&ahb_gates 6>;
+			#dma-cells = <2>;
+		};
+
 		spi0: spi@01c05000 {
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c05000 0x1000>;
-- 
2.0.4
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[PATCH v3 5/8] ARM: sun7i: dt: Add node to represent the DMA controller

[Emilio López]

The A20 SoC has a sun4i-compatible DMA controller. Let's add a node to
represent it on the device tree.

Signed-off-by: Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
Reviewed-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---

Changes from v2:
 * Fix whitespace
 * Collect tag from Chen-Yu

 arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 01e9466..510b5a8 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -423,6 +423,14 @@
 			interrupts = <0 0 4>;
 		};
 
+		dma: dma-controller@01c02000 {
+			compatible = "allwinner,sun4i-a10-dma";
+			reg = <0x01c02000 0x1000>;
+			interrupts = <0 27 4>;
+			clocks = <&ahb_gates 6>;
+			#dma-cells = <2>;
+		};
+
 		spi0: spi@01c05000 {
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c05000 0x1000>;
-- 
2.0.4
--
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[PATCH v3 6/8] ARM: sun4i: dt: enable DMA on SPI

[Emilio López]

All of our SPI controllers support DMA transfers, so let's add the
properties here so they can be used when it's best to do so.

Signed-off-by: Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
Reviewed-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---

Changes from v2:
 * Collect tag from Chen-Yu

 arch/arm/boot/dts/sun4i-a10.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 5c6791a..b6a491b 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -353,6 +353,8 @@
 			interrupts = <10>;
 			clocks = <&ahb_gates 20>, <&spi0_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 27>, <&dma 1 26>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -364,6 +366,8 @@
 			interrupts = <11>;
 			clocks = <&ahb_gates 21>, <&spi1_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 9>, <&dma 1 8>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -459,6 +463,8 @@
 			interrupts = <12>;
 			clocks = <&ahb_gates 22>, <&spi2_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 29>, <&dma 1 28>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -498,6 +504,8 @@
 			interrupts = <50>;
 			clocks = <&ahb_gates 23>, <&spi3_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 31>, <&dma 1 30>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
-- 
2.0.4
--
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[PATCH v3 7/8] ARM: sun5i: dt: enable DMA on SPI

[Emilio López]

All of our SPI controllers support DMA transfers, so let's add the
properties here so they can be used when it's best to do so.

Signed-off-by: Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
Reviewed-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---

Changes from v2:
 * Collect tag from Chen-Yu

 arch/arm/boot/dts/sun5i-a10s.dtsi | 6 ++++++
 arch/arm/boot/dts/sun5i-a13.dtsi  | 6 ++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 8b5a27c..2ee786a 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -314,6 +314,8 @@
 			interrupts = <10>;
 			clocks = <&ahb_gates 20>, <&spi0_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 27>, <&dma 1 26>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -325,6 +327,8 @@
 			interrupts = <11>;
 			clocks = <&ahb_gates 21>, <&spi1_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 9>, <&dma 1 8>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -411,6 +415,8 @@
 			interrupts = <12>;
 			clocks = <&ahb_gates 22>, <&spi2_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 29>, <&dma 1 28>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 139f4ac..6e0823b 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -312,6 +312,8 @@
 			interrupts = <10>;
 			clocks = <&ahb_gates 20>, <&spi0_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 27>, <&dma 1 26>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -323,6 +325,8 @@
 			interrupts = <11>;
 			clocks = <&ahb_gates 21>, <&spi1_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 9>, <&dma 1 8>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -384,6 +388,8 @@
 			interrupts = <12>;
 			clocks = <&ahb_gates 22>, <&spi2_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 29>, <&dma 1 28>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
-- 
2.0.4
--
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[PATCH v3 8/8] ARM: sun7i: dt: enable DMA on SPI

[Emilio López]

All of our SPI controllers support DMA transfers, so let's add the
properties here so they can be used when it's best to do so.

Signed-off-by: Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
Reviewed-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---

Changes from v2:
 * Collect tag from Chen-Yu

 arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 510b5a8..ecdc873 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -437,6 +437,8 @@
 			interrupts = <0 10 4>;
 			clocks = <&ahb_gates 20>, <&spi0_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 27>, <&dma 1 26>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -448,6 +450,8 @@
 			interrupts = <0 11 4>;
 			clocks = <&ahb_gates 21>, <&spi1_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 9>, <&dma 1 8>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -543,6 +547,8 @@
 			interrupts = <0 12 4>;
 			clocks = <&ahb_gates 22>, <&spi2_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 29>, <&dma 1 28>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -582,6 +588,8 @@
 			interrupts = <0 50 4>;
 			clocks = <&ahb_gates 23>, <&spi3_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 31>, <&dma 1 30>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
-- 
2.0.4
--
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