[PATCH 0/1] ARM: spi supports 32bytes buffer for DUAL and QUAD

[PATCH 0/1] ARM: spi supports 32bytes buffer for DUAL and QUAD

[Cao Minh Hiep]

From: Hiep Cao Minh <cm-hiep@jinso.co.jp>

Hi,

This patch will improve the DUAL and QUAD's performance of SPI,
that supported for GEN2 r8a7790 SOC in PIO mode. 
It sends/receives each 32bytes of data instead of each byte data 
as current situation.

This patch was developed based on the Mainline v4.9-rc3 and have 
tested on the Lager board.

Please consider the following patches for the r8a7790 Soc.

Thank you!

Cao Minh Hiep

Hiep Cao Minh (1):
  ARM:spi supports 32bytes buffer for DUAL and QUAD

 drivers/spi/spi-rspi.c | 52 +++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 49 insertions(+), 3 deletions(-)

-- 
1.9.1

[PATCH 1/1] ARM: spi supports 32bytes buffer for DUAL and QUAD

[Cao Minh Hiep]

From: Hiep Cao Minh <cm-hiep-HEF513clHfp3+QwDJ9on6Q@public.gmane.org>

This patch supports 32bytes of buffer for DUAL and QUAD in QSPI by
Using Transmit/Receive Buffer Data Triggering Number.
In order to improve the DUAL and QUAD's performance of SPI 
while transferring data in PIO mode, it sends/receives each 32bytes 
data instead of each byte data as current situation.

Signed-off-by: Hiep Cao Minh <cm-hiep-HEF513clHfp3+QwDJ9on6Q@public.gmane.org>
---
 drivers/spi/spi-rspi.c | 52 +++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 49 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index a816f07..fb12bc5 100644
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -413,7 +413,7 @@ static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
 	return n;
 }
 
-static void qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
+static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
 {
 	unsigned int n;
 
@@ -428,6 +428,7 @@ static void qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
 		qspi_update(rspi, SPBFCR_RXTRG_MASK,
 			     SPBFCR_RXTRG_1B, QSPI_SPBFCR);
 	}
+	return n;
 }
 
 #define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
@@ -514,6 +515,51 @@ static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
 	return 0;
 }
 
+static int rspi_pio_transfer_in_or_our(struct rspi_data *rspi, const u8 *tx,
+				       u8 *rx, unsigned int n)
+{
+	unsigned int i, len;
+	int ret;
+
+	while (n > 0) {
+		if (tx) {
+			len = qspi_set_send_trigger(rspi, n);
+			if (len == QSPI_BUFFER_SIZE) {
+				ret = rspi_wait_for_tx_empty(rspi);
+				if (ret < 0) {
+					dev_err(&rspi->master->dev, "transmit timeout\n");
+					return ret;
+				}
+				for (i = 0; i < len; i++)
+					rspi_write_data(rspi, *tx++);
+			} else {
+				ret = rspi_pio_transfer(rspi, tx, NULL, n);
+				if (ret < 0)
+					return ret;
+			}
+		}
+		if (rx) {
+			len = qspi_set_receive_trigger(rspi, n);
+			if (len == QSPI_BUFFER_SIZE) {
+				ret = rspi_wait_for_rx_full(rspi);
+				if (ret < 0) {
+					dev_err(&rspi->master->dev, "receive timeout\n");
+					return ret;
+				}
+				for (i = 0; i < len; i++)
+					*rx++ = rspi_read_data(rspi);
+			} else {
+				ret = rspi_pio_transfer(rspi, NULL, rx, n);
+				if (ret < 0)
+					return ret;
+				*rx++ = ret;
+			}
+		}
+		n -= len;
+	}
+	return 0;
+}
+
 static void rspi_dma_complete(void *arg)
 {
 	struct rspi_data *rspi = arg;
@@ -793,7 +839,7 @@ static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
 			return ret;
 	}
 
-	ret = rspi_pio_transfer(rspi, xfer->tx_buf, NULL, xfer->len);
+	ret = rspi_pio_transfer_in_or_our(rspi, xfer->tx_buf, NULL, xfer->len);
 	if (ret < 0)
 		return ret;
 
@@ -811,7 +857,7 @@ static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
 			return ret;
 	}
 
-	return rspi_pio_transfer(rspi, NULL, xfer->rx_buf, xfer->len);
+	return rspi_pio_transfer_in_or_our(rspi, NULL, xfer->rx_buf, xfer->len);
 }
 
 static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,
-- 
1.9.1

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Re: [PATCH 0/1] ARM: spi supports 32bytes buffer for DUAL and QUAD

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 672 bytes --]

On Fri, Nov 04, 2016 at 05:38:53PM +0900, Cao Minh Hiep wrote:
> From: Hiep Cao Minh <cm-hiep-HEF513clHfp3+QwDJ9on6Q@public.gmane.org>
> 
> Hi,
> 
> This patch will improve the DUAL and QUAD's performance of SPI,
> that supported for GEN2 r8a7790 SOC in PIO mode. 
> It sends/receives each 32bytes of data instead of each byte data 
> as current situation.

Please don't send cover letters for single patches, if there is anything
that needs saying put it in the changelog of the patch or after the ---
if it's administrative stuff.  This reduces mail volume and ensures that 
any important information is recorded in the changelog rather than being
lost. 

[-- Attachment #2: signature.asc --]
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Re: [PATCH 1/1] ARM: spi supports 32bytes buffer for DUAL and QUAD

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 370 bytes --]

On Fri, Nov 04, 2016 at 05:38:54PM +0900, Cao Minh Hiep wrote:
> From: Hiep Cao Minh <cm-hiep@jinso.co.jp>
> 
> This patch supports 32bytes of buffer for DUAL and QUAD in QSPI by
> Using Transmit/Receive Buffer Data Triggering Number.

Please use subject lines matching the style for the subsystem.  This
makes it easier for people to identify relevant patches.

[-- Attachment #2: signature.asc --]
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Applied "spi: rspi: supports 32bytes buffer for DUAL and QUAD" to the spi tree

[Mark Brown]

The patch

   spi: rspi: supports 32bytes buffer for DUAL and QUAD

has been applied to the spi tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 3be09bec42a800d4f8ead8119c462f3eb4fad435 Mon Sep 17 00:00:00 2001
From: Hiep Cao Minh <cm-hiep@jinso.co.jp>
Date: Fri, 4 Nov 2016 17:38:54 +0900
Subject: [PATCH] spi: rspi: supports 32bytes buffer for DUAL and QUAD

This patch supports 32bytes of buffer for DUAL and QUAD in QSPI by
Using Transmit/Receive Buffer Data Triggering Number.
In order to improve the DUAL and QUAD's performance of SPI
while transferring data in PIO mode, it sends/receives each 32bytes
data instead of each byte data as current situation.

Signed-off-by: Hiep Cao Minh <cm-hiep@jinso.co.jp>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/spi/spi-rspi.c | 52 +++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 49 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index a816f07e168e..3bab75ab1b25 100644
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -413,7 +413,7 @@ static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
 	return n;
 }
 
-static void qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
+static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
 {
 	unsigned int n;
 
@@ -428,6 +428,7 @@ static void qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
 		qspi_update(rspi, SPBFCR_RXTRG_MASK,
 			     SPBFCR_RXTRG_1B, QSPI_SPBFCR);
 	}
+	return n;
 }
 
 #define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
@@ -514,6 +515,51 @@ static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
 	return 0;
 }
 
+static int rspi_pio_transfer_in_or_our(struct rspi_data *rspi, const u8 *tx,
+				       u8 *rx, unsigned int n)
+{
+	unsigned int i, len;
+	int ret;
+
+	while (n > 0) {
+		if (tx) {
+			len = qspi_set_send_trigger(rspi, n);
+			if (len == QSPI_BUFFER_SIZE) {
+				ret = rspi_wait_for_tx_empty(rspi);
+				if (ret < 0) {
+					dev_err(&rspi->master->dev, "transmit timeout\n");
+					return ret;
+				}
+				for (i = 0; i < len; i++)
+					rspi_write_data(rspi, *tx++);
+			} else {
+				ret = rspi_pio_transfer(rspi, tx, NULL, n);
+				if (ret < 0)
+					return ret;
+			}
+		}
+		if (rx) {
+			len = qspi_set_receive_trigger(rspi, n);
+			if (len == QSPI_BUFFER_SIZE) {
+				ret = rspi_wait_for_rx_full(rspi);
+				if (ret < 0) {
+					dev_err(&rspi->master->dev, "receive timeout\n");
+					return ret;
+				}
+				for (i = 0; i < len; i++)
+					*rx++ = rspi_read_data(rspi);
+			} else {
+				ret = rspi_pio_transfer(rspi, NULL, rx, n);
+				if (ret < 0)
+					return ret;
+				*rx++ = ret;
+			}
+		}
+		n -= len;
+	}
+	return 0;
+}
+
 static void rspi_dma_complete(void *arg)
 {
 	struct rspi_data *rspi = arg;
@@ -793,7 +839,7 @@ static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
 			return ret;
 	}
 
-	ret = rspi_pio_transfer(rspi, xfer->tx_buf, NULL, xfer->len);
+	ret = rspi_pio_transfer_in_or_our(rspi, xfer->tx_buf, NULL, xfer->len);
 	if (ret < 0)
 		return ret;
 
@@ -811,7 +857,7 @@ static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
 			return ret;
 	}
 
-	return rspi_pio_transfer(rspi, NULL, xfer->rx_buf, xfer->len);
+	return rspi_pio_transfer_in_or_our(rspi, NULL, xfer->rx_buf, xfer->len);
 }
 
 static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,
-- 
2.10.1

Re: [PATCH 1/1] ARM: spi supports 32bytes buffer for DUAL and QUAD

[Niklas Söderlund]

Hi Cao,

On 2016-11-04 17:38:54 +0900, Cao Minh Hiep wrote:
> From: Hiep Cao Minh <cm-hiep-HEF513clHfp3+QwDJ9on6Q@public.gmane.org>
> 
> This patch supports 32bytes of buffer for DUAL and QUAD in QSPI by
> Using Transmit/Receive Buffer Data Triggering Number.
> In order to improve the DUAL and QUAD's performance of SPI 
> while transferring data in PIO mode, it sends/receives each 32bytes 
> data instead of each byte data as current situation.
> 
> Signed-off-by: Hiep Cao Minh <cm-hiep-HEF513clHfp3+QwDJ9on6Q@public.gmane.org>
> ---
>  drivers/spi/spi-rspi.c | 52 +++++++++++++++++++++++++++++++++++++++++++++++---
>  1 file changed, 49 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
> index a816f07..fb12bc5 100644
> --- a/drivers/spi/spi-rspi.c
> +++ b/drivers/spi/spi-rspi.c
> @@ -413,7 +413,7 @@ static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
>  	return n;
>  }
>  
> -static void qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
> +static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
>  {
>  	unsigned int n;
>  
> @@ -428,6 +428,7 @@ static void qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
>  		qspi_update(rspi, SPBFCR_RXTRG_MASK,
>  			     SPBFCR_RXTRG_1B, QSPI_SPBFCR);
>  	}
> +	return n;
>  }
>  
>  #define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
> @@ -514,6 +515,51 @@ static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
>  	return 0;
>  }
>  
> +static int rspi_pio_transfer_in_or_our(struct rspi_data *rspi, const u8 *tx,
> +				       u8 *rx, unsigned int n)

Nitpicking, s/rspi_pio_transfer_in_or_our/rspi_pio_transfer_in_or_out/ 
or am I missing something?

> +{
> +	unsigned int i, len;
> +	int ret;
> +
> +	while (n > 0) {
> +		if (tx) {
> +			len = qspi_set_send_trigger(rspi, n);
> +			if (len == QSPI_BUFFER_SIZE) {
> +				ret = rspi_wait_for_tx_empty(rspi);
> +				if (ret < 0) {
> +					dev_err(&rspi->master->dev, "transmit timeout\n");
> +					return ret;
> +				}
> +				for (i = 0; i < len; i++)
> +					rspi_write_data(rspi, *tx++);
> +			} else {
> +				ret = rspi_pio_transfer(rspi, tx, NULL, n);
> +				if (ret < 0)
> +					return ret;
> +			}
> +		}
> +		if (rx) {
> +			len = qspi_set_receive_trigger(rspi, n);
> +			if (len == QSPI_BUFFER_SIZE) {
> +				ret = rspi_wait_for_rx_full(rspi);
> +				if (ret < 0) {
> +					dev_err(&rspi->master->dev, "receive timeout\n");
> +					return ret;
> +				}
> +				for (i = 0; i < len; i++)
> +					*rx++ = rspi_read_data(rspi);
> +			} else {
> +				ret = rspi_pio_transfer(rspi, NULL, rx, n);
> +				if (ret < 0)
> +					return ret;
> +				*rx++ = ret;
> +			}
> +		}
> +		n -= len;
> +	}
> +	return 0;
> +}
> +
>  static void rspi_dma_complete(void *arg)
>  {
>  	struct rspi_data *rspi = arg;
> @@ -793,7 +839,7 @@ static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
>  			return ret;
>  	}
>  
> -	ret = rspi_pio_transfer(rspi, xfer->tx_buf, NULL, xfer->len);
> +	ret = rspi_pio_transfer_in_or_our(rspi, xfer->tx_buf, NULL, xfer->len);
>  	if (ret < 0)
>  		return ret;
>  
> @@ -811,7 +857,7 @@ static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
>  			return ret;
>  	}
>  
> -	return rspi_pio_transfer(rspi, NULL, xfer->rx_buf, xfer->len);
> +	return rspi_pio_transfer_in_or_our(rspi, NULL, xfer->rx_buf, xfer->len);
>  }
>  
>  static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,
> -- 
> 1.9.1
> 

-- 
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Niklas Söderlund
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Re: [PATCH 0/1] ARM: spi supports 32bytes buffer for DUAL and QUAD

[Hiep Cao Minh]

Hi Mark


On 11/05/2016 12:49 AM, Mark Brown wrote:
> On Fri, Nov 04, 2016 at 05:38:53PM +0900, Cao Minh Hiep wrote:
>> From: Hiep Cao Minh <cm-hiep@jinso.co.jp>
>>
>> Hi,
>>
>> This patch will improve the DUAL and QUAD's performance of SPI,
>> that supported for GEN2 r8a7790 SOC in PIO mode.
>> It sends/receives each 32bytes of data instead of each byte data
>> as current situation.
> Please don't send cover letters for single patches, if there is anything
> that needs saying put it in the changelog of the patch or after the ---
> if it's administrative stuff.  This reduces mail volume and ensures that
> any important information is recorded in the changelog rather than being
> lost.
Thanks, I will do it next time.

Best regards,
Jinzai solution Inc.
Hiep.

Re: Applied "spi: rspi: supports 32bytes buffer for DUAL and QUAD" to the spi tree

[Hiep Cao Minh]

Hi Mark,

On 11/05/2016 02:23 AM, Mark Brown wrote:
> The patch
>
>     spi: rspi: supports 32bytes buffer for DUAL and QUAD
>
> has been applied to the spi tree at
>
>     git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git

Thanks,

Best regards,
Jinzai Solution Inc.
Hiep.

> All being well this means that it will be integrated into the linux-next
> tree (usually sometime in the next 24 hours) and sent to Linus during
> the next merge window (or sooner if it is a bug fix), however if
> problems are discovered then the patch may be dropped or reverted.
>
> You may get further e-mails resulting from automated or manual testing
> and review of the tree, please engage with people reporting problems and
> send followup patches addressing any issues that are reported if needed.
>
> If any updates are required or you are submitting further changes they
> should be sent as incremental updates against current git, existing
> patches will not be replaced.
>
> Please add any relevant lists and maintainers to the CCs when replying
> to this mail.
>
> Thanks,
> Mark
>
> >From 3be09bec42a800d4f8ead8119c462f3eb4fad435 Mon Sep 17 00:00:00 2001
> From: Hiep Cao Minh <cm-hiep-HEF513clHfp3+QwDJ9on6Q@public.gmane.org>
> Date: Fri, 4 Nov 2016 17:38:54 +0900
> Subject: [PATCH] spi: rspi: supports 32bytes buffer for DUAL and QUAD
>
> This patch supports 32bytes of buffer for DUAL and QUAD in QSPI by
> Using Transmit/Receive Buffer Data Triggering Number.
> In order to improve the DUAL and QUAD's performance of SPI
> while transferring data in PIO mode, it sends/receives each 32bytes
> data instead of each byte data as current situation.
>
> Signed-off-by: Hiep Cao Minh <cm-hiep-HEF513clHfp3+QwDJ9on6Q@public.gmane.org>
> Signed-off-by: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> ---
>   drivers/spi/spi-rspi.c | 52 +++++++++++++++++++++++++++++++++++++++++++++++---
>   1 file changed, 49 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
> index a816f07e168e..3bab75ab1b25 100644
> --- a/drivers/spi/spi-rspi.c
> +++ b/drivers/spi/spi-rspi.c
> @@ -413,7 +413,7 @@ static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
>   	return n;
>   }
>   
> -static void qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
> +static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
>   {
>   	unsigned int n;
>   
> @@ -428,6 +428,7 @@ static void qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
>   		qspi_update(rspi, SPBFCR_RXTRG_MASK,
>   			     SPBFCR_RXTRG_1B, QSPI_SPBFCR);
>   	}
> +	return n;
>   }
>   
>   #define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
> @@ -514,6 +515,51 @@ static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
>   	return 0;
>   }
>   
> +static int rspi_pio_transfer_in_or_our(struct rspi_data *rspi, const u8 *tx,
> +				       u8 *rx, unsigned int n)
> +{
> +	unsigned int i, len;
> +	int ret;
> +
> +	while (n > 0) {
> +		if (tx) {
> +			len = qspi_set_send_trigger(rspi, n);
> +			if (len == QSPI_BUFFER_SIZE) {
> +				ret = rspi_wait_for_tx_empty(rspi);
> +				if (ret < 0) {
> +					dev_err(&rspi->master->dev, "transmit timeout\n");
> +					return ret;
> +				}
> +				for (i = 0; i < len; i++)
> +					rspi_write_data(rspi, *tx++);
> +			} else {
> +				ret = rspi_pio_transfer(rspi, tx, NULL, n);
> +				if (ret < 0)
> +					return ret;
> +			}
> +		}
> +		if (rx) {
> +			len = qspi_set_receive_trigger(rspi, n);
> +			if (len == QSPI_BUFFER_SIZE) {
> +				ret = rspi_wait_for_rx_full(rspi);
> +				if (ret < 0) {
> +					dev_err(&rspi->master->dev, "receive timeout\n");
> +					return ret;
> +				}
> +				for (i = 0; i < len; i++)
> +					*rx++ = rspi_read_data(rspi);
> +			} else {
> +				ret = rspi_pio_transfer(rspi, NULL, rx, n);
> +				if (ret < 0)
> +					return ret;
> +				*rx++ = ret;
> +			}
> +		}
> +		n -= len;
> +	}
> +	return 0;
> +}
> +
>   static void rspi_dma_complete(void *arg)
>   {
>   	struct rspi_data *rspi = arg;
> @@ -793,7 +839,7 @@ static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
>   			return ret;
>   	}
>   
> -	ret = rspi_pio_transfer(rspi, xfer->tx_buf, NULL, xfer->len);
> +	ret = rspi_pio_transfer_in_or_our(rspi, xfer->tx_buf, NULL, xfer->len);
>   	if (ret < 0)
>   		return ret;
>   
> @@ -811,7 +857,7 @@ static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
>   			return ret;
>   	}
>   
> -	return rspi_pio_transfer(rspi, NULL, xfer->rx_buf, xfer->len);
> +	return rspi_pio_transfer_in_or_our(rspi, NULL, xfer->rx_buf, xfer->len);
>   }
>   
>   static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,

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Re: [PATCH 1/1] ARM: spi supports 32bytes buffer for DUAL and QUAD

[Hiep Cao Minh]

Hi Niklas,

Thanks for your comment.

On 11/05/2016 04:32 PM, Niklas Söderlund wrote:
> Hi Cao,
>
> On 2016-11-04 17:38:54 +0900, Cao Minh Hiep wrote:
>> From: Hiep Cao Minh <cm-hiep@jinso.co.jp>
>>
>> This patch supports 32bytes of buffer for DUAL and QUAD in QSPI by
>> Using Transmit/Receive Buffer Data Triggering Number.
>> In order to improve the DUAL and QUAD's performance of SPI
>> while transferring data in PIO mode, it sends/receives each 32bytes
>> data instead of each byte data as current situation.
>>
>> Signed-off-by: Hiep Cao Minh <cm-hiep@jinso.co.jp>
>> ---
>>   drivers/spi/spi-rspi.c | 52 +++++++++++++++++++++++++++++++++++++++++++++++---
>>   1 file changed, 49 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
>> index a816f07..fb12bc5 100644
>> --- a/drivers/spi/spi-rspi.c
>> +++ b/drivers/spi/spi-rspi.c
>> @@ -413,7 +413,7 @@ static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
>>   	return n;
>>   }
>>   
>> -static void qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
>> +static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
>>   {
>>   	unsigned int n;
>>   
>> @@ -428,6 +428,7 @@ static void qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
>>   		qspi_update(rspi, SPBFCR_RXTRG_MASK,
>>   			     SPBFCR_RXTRG_1B, QSPI_SPBFCR);
>>   	}
>> +	return n;
>>   }
>>   
>>   #define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
>> @@ -514,6 +515,51 @@ static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
>>   	return 0;
>>   }
>>   
>> +static int rspi_pio_transfer_in_or_our(struct rspi_data *rspi, const u8 *tx,
>> +				       u8 *rx, unsigned int n)
> Nitpicking, s/rspi_pio_transfer_in_or_our/rspi_pio_transfer_in_or_out/
> or am I missing something?
You're right!. It should be "rspi_pio_transfer_in_or_out"
I'll update it in an other patch.

Thanks.
Jinzai Solution Inc,
Hiep.