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* [PATCH 00/12] XSPI mode for LS1021A DSPI
@ 2018-06-20  7:34 Esben Haabendal
  2018-06-20  7:34 ` [PATCH 01/12] spi: spi-fsl-dspi: Drop unreachable else if statement Esben Haabendal
                   ` (11 more replies)
  0 siblings, 12 replies; 16+ messages in thread
From: Esben Haabendal @ 2018-06-20  7:34 UTC (permalink / raw)
  To: Mark Brown, linux-spi
  Cc: Kurt Kanzenbach, Angelo Dureghello, Nikita Yushchenko,
	Sanchayan Maity, Yuan Yao, linux-kernel, Esben Haabendal

From: Esben Haabendal <eha@deif.com>

This patch series contains a number of fixes and cleanups for the spi-fsl-dspi
driver (commit 1-7), and on top of that, implementation of XSPI mode for
LS1021A allowing for SPI transfers larger than 16 bits (commit 8-12).

User visible changes (improvements) are:

* Support for all transfer sizes between 4 and 16, not just 4 (which I believe
  were broken anyway), 8 and 16 bits per word.  

* Full support for transfer->cs_change flag.  Setting cs_change in last
  transfer leaves CS asserted.

* Support for all transfers sizes between 4 and 32 bits per word for LS1021A.

The XSPI mode can be trivially enabled for other target using TCQF mode.
Enable for targets using EOQ mode requires additional work due to the split
of TX FIFO into command and data FIFO.

If you like, I will happily squash the last 5 commits into a single XSPI mode
commit.

Esben Haabendal (12):
  spi: spi-fsl-dspi: Drop unreachable else if statement
  spi: spi-fsl-dspi: Drop unneeded use of dataflags bits
  spi: spi-fsl-dspi: Fix per transfer cs_change handling
  spi: spi-fsl-dspi: Simplify transfer counter handling
  spi: spi-fsl-dspi: Support 4 to 16 bits per word transfers
  spi: spi-fsl-dspi: Fixup regmap configuration
  spi: spi-fsl-dspi: Fix MCR register handling
  spi: spi-fsl-dspi: Add support for XSPI mode registers
  spi: spi-fsl-dspi: Framesize control for XSPI mode
  spi: spi-fsl-dspi: XSPI FIFO handling (in TCFQ mode)
  spi: spi-fsl-dspi: Advertise 32 bit for XSPI mode
  spi: spi-fsl-dspi: Enable extended SPI mode

 drivers/spi/spi-fsl-dspi.c | 458 ++++++++++++++++++++-----------------
 1 file changed, 250 insertions(+), 208 deletions(-)

-- 
2.17.1

^ permalink raw reply	[flat|nested] 16+ messages in thread

end of thread, other threads:[~2018-06-20 13:40 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-06-20  7:34 [PATCH 00/12] XSPI mode for LS1021A DSPI Esben Haabendal
2018-06-20  7:34 ` [PATCH 01/12] spi: spi-fsl-dspi: Drop unreachable else if statement Esben Haabendal
2018-06-20  8:40   ` Martin Hundebøll
2018-06-20  7:34 ` [PATCH 02/12] spi: spi-fsl-dspi: Drop unneeded use of dataflags bits Esben Haabendal
2018-06-20  7:34 ` [PATCH 03/12] spi: spi-fsl-dspi: Fix per transfer cs_change handling Esben Haabendal
2018-06-20 13:27   ` Mark Brown
2018-06-20 13:40     ` Esben Haabendal
2018-06-20  7:34 ` [PATCH 04/12] spi: spi-fsl-dspi: Simplify transfer counter handling Esben Haabendal
2018-06-20  7:34 ` [PATCH 05/12] spi: spi-fsl-dspi: Support 4 to 16 bits per word transfers Esben Haabendal
2018-06-20  7:34 ` [PATCH 06/12] spi: spi-fsl-dspi: Fixup regmap configuration Esben Haabendal
2018-06-20  7:34 ` [PATCH 07/12] spi: spi-fsl-dspi: Fix MCR register handling Esben Haabendal
2018-06-20  7:34 ` [PATCH 08/12] spi: spi-fsl-dspi: Add support for XSPI mode registers Esben Haabendal
2018-06-20  7:34 ` [PATCH 09/12] spi: spi-fsl-dspi: Framesize control for XSPI mode Esben Haabendal
2018-06-20  7:34 ` [PATCH 10/12] spi: spi-fsl-dspi: XSPI FIFO handling (in TCFQ mode) Esben Haabendal
2018-06-20  7:34 ` [PATCH 11/12] spi: spi-fsl-dspi: Advertise 32 bit for XSPI mode Esben Haabendal
2018-06-20  7:34 ` [PATCH 12/12] spi: spi-fsl-dspi: Enable extended SPI mode Esben Haabendal

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