[PATCH 0/5] Add support for STM32F4 SPI

[PATCH 0/5] Add support for STM32F4 SPI

[cezary.gapinski]

From: Cezary Gapinski <cezary.gapinski@gmail.com>

This series of patches adds support for first generation of SPI interface
for STM32F4 family.

This version of driver is mostly different to STM32H7 one. Based on linux
kernel I2C drivers for STM32 where drivers were splited into STM32F4 and
STM32F7 family the same approach seems to be sufficient for SPI STM32
drivers. Therefore STM32H7 driver was moved to spi-stm32h7.c file and
register and functions were renamed to be more specific to STM32H7.

For current version master mode with full-duplex and 8/16 bit data frame
format are supported. There is no TX and RX FIFOs like in STM32H7.
DMA capabilility is supported for messages longer than arbitrary number
of bytes (that is set already to 16 bytes) when TX and RX channels are
set at the same time.

Cezary Gapinski (5):
  spi: stm32: rename STM32 SPI registers and functions to STM32H7
  spi: stm32: rename spi-stm32 to spi-stm32h7
  spi: stm32: add driver for STM32F4 controller
  ARM: dts: stm32: add SPI support on STM32F429 SoC
  spi: stm32: add description about STM32F4 bindings

 .../devicetree/bindings/spi/spi-stm32.txt          |    9 +-
 arch/arm/boot/dts/stm32f429.dtsi                   |   60 +
 drivers/spi/Kconfig                                |   18 +-
 drivers/spi/Makefile                               |    3 +-
 drivers/spi/spi-stm32.c                            | 1322 -------------------
 drivers/spi/spi-stm32f4.c                          | 1002 +++++++++++++++
 drivers/spi/spi-stm32h7.c                          | 1340 ++++++++++++++++++++
 7 files changed, 2424 insertions(+), 1330 deletions(-)
 delete mode 100644 drivers/spi/spi-stm32.c
 create mode 100644 drivers/spi/spi-stm32f4.c
 create mode 100644 drivers/spi/spi-stm32h7.c

-- 
2.7.4

[PATCH 1/5] spi: stm32: rename STM32 SPI registers and functions to STM32H7

[cezary.gapinski]

From: Cezary Gapinski <cezary.gapinski@gmail.com>

Rename STM32 SPI registers and functions to be related to STM32H7 SPI
driver and not STM32 generally.

Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com>
---
 drivers/spi/spi-stm32.c | 662 +++++++++++++++++++++++++-----------------------
 1 file changed, 340 insertions(+), 322 deletions(-)

diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index ad1e55d..eb4d93e 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -33,97 +33,97 @@
 
 #define DRIVER_NAME "spi_stm32"
 
-/* STM32 SPI registers */
-#define STM32_SPI_CR1		0x00
-#define STM32_SPI_CR2		0x04
-#define STM32_SPI_CFG1		0x08
-#define STM32_SPI_CFG2		0x0C
-#define STM32_SPI_IER		0x10
-#define STM32_SPI_SR		0x14
-#define STM32_SPI_IFCR		0x18
-#define STM32_SPI_TXDR		0x20
-#define STM32_SPI_RXDR		0x30
-#define STM32_SPI_I2SCFGR	0x50
-
-/* STM32_SPI_CR1 bit fields */
-#define SPI_CR1_SPE		BIT(0)
-#define SPI_CR1_MASRX		BIT(8)
-#define SPI_CR1_CSTART		BIT(9)
-#define SPI_CR1_CSUSP		BIT(10)
-#define SPI_CR1_HDDIR		BIT(11)
-#define SPI_CR1_SSI		BIT(12)
-
-/* STM32_SPI_CR2 bit fields */
-#define SPI_CR2_TSIZE_SHIFT	0
-#define SPI_CR2_TSIZE		GENMASK(15, 0)
-
-/* STM32_SPI_CFG1 bit fields */
-#define SPI_CFG1_DSIZE_SHIFT	0
-#define SPI_CFG1_DSIZE		GENMASK(4, 0)
-#define SPI_CFG1_FTHLV_SHIFT	5
-#define SPI_CFG1_FTHLV		GENMASK(8, 5)
-#define SPI_CFG1_RXDMAEN	BIT(14)
-#define SPI_CFG1_TXDMAEN	BIT(15)
-#define SPI_CFG1_MBR_SHIFT	28
-#define SPI_CFG1_MBR		GENMASK(30, 28)
-#define SPI_CFG1_MBR_MIN	0
-#define SPI_CFG1_MBR_MAX	(GENMASK(30, 28) >> 28)
-
-/* STM32_SPI_CFG2 bit fields */
-#define SPI_CFG2_MIDI_SHIFT	4
-#define SPI_CFG2_MIDI		GENMASK(7, 4)
-#define SPI_CFG2_COMM_SHIFT	17
-#define SPI_CFG2_COMM		GENMASK(18, 17)
-#define SPI_CFG2_SP_SHIFT	19
-#define SPI_CFG2_SP		GENMASK(21, 19)
-#define SPI_CFG2_MASTER		BIT(22)
-#define SPI_CFG2_LSBFRST	BIT(23)
-#define SPI_CFG2_CPHA		BIT(24)
-#define SPI_CFG2_CPOL		BIT(25)
-#define SPI_CFG2_SSM		BIT(26)
-#define SPI_CFG2_AFCNTR		BIT(31)
-
-/* STM32_SPI_IER bit fields */
-#define SPI_IER_RXPIE		BIT(0)
-#define SPI_IER_TXPIE		BIT(1)
-#define SPI_IER_DXPIE		BIT(2)
-#define SPI_IER_EOTIE		BIT(3)
-#define SPI_IER_TXTFIE		BIT(4)
-#define SPI_IER_OVRIE		BIT(6)
-#define SPI_IER_MODFIE		BIT(9)
-#define SPI_IER_ALL		GENMASK(10, 0)
-
-/* STM32_SPI_SR bit fields */
-#define SPI_SR_RXP		BIT(0)
-#define SPI_SR_TXP		BIT(1)
-#define SPI_SR_EOT		BIT(3)
-#define SPI_SR_OVR		BIT(6)
-#define SPI_SR_MODF		BIT(9)
-#define SPI_SR_SUSP		BIT(11)
-#define SPI_SR_RXPLVL_SHIFT	13
-#define SPI_SR_RXPLVL		GENMASK(14, 13)
-#define SPI_SR_RXWNE		BIT(15)
-
-/* STM32_SPI_IFCR bit fields */
-#define SPI_IFCR_ALL		GENMASK(11, 3)
-
-/* STM32_SPI_I2SCFGR bit fields */
-#define SPI_I2SCFGR_I2SMOD	BIT(0)
-
-/* SPI Master Baud Rate min/max divisor */
-#define SPI_MBR_DIV_MIN		(2 << SPI_CFG1_MBR_MIN)
-#define SPI_MBR_DIV_MAX		(2 << SPI_CFG1_MBR_MAX)
-
-/* SPI Communication mode */
-#define SPI_FULL_DUPLEX		0
-#define SPI_SIMPLEX_TX		1
-#define SPI_SIMPLEX_RX		2
-#define SPI_HALF_DUPLEX		3
-
-#define SPI_1HZ_NS		1000000000
+/* STM32H7 SPI registers */
+#define STM32H7_SPI_CR1			0x00
+#define STM32H7_SPI_CR2			0x04
+#define STM32H7_SPI_CFG1		0x08
+#define STM32H7_SPI_CFG2		0x0C
+#define STM32H7_SPI_IER			0x10
+#define STM32H7_SPI_SR			0x14
+#define STM32H7_SPI_IFCR		0x18
+#define STM32H7_SPI_TXDR		0x20
+#define STM32H7_SPI_RXDR		0x30
+#define STM32H7_SPI_I2SCFGR		0x50
+
+/* STM32H7_SPI_CR1 bit fields */
+#define STM32H7_SPI_CR1_SPE		BIT(0)
+#define STM32H7_SPI_CR1_MASRX		BIT(8)
+#define STM32H7_SPI_CR1_CSTART		BIT(9)
+#define STM32H7_SPI_CR1_CSUSP		BIT(10)
+#define STM32H7_SPI_CR1_HDDIR		BIT(11)
+#define STM32H7_SPI_CR1_SSI		BIT(12)
+
+/* STM32H7_SPI_CR2 bit fields */
+#define STM32H7_SPI_CR2_TSIZE_SHIFT	0
+#define STM32H7_SPI_CR2_TSIZE		GENMASK(15, 0)
+
+/* STM32H7_SPI_CFG1 bit fields */
+#define STM32H7_SPI_CFG1_DSIZE_SHIFT	0
+#define STM32H7_SPI_CFG1_DSIZE		GENMASK(4, 0)
+#define STM32H7_SPI_CFG1_FTHLV_SHIFT	5
+#define STM32H7_SPI_CFG1_FTHLV		GENMASK(8, 5)
+#define STM32H7_SPI_CFG1_RXDMAEN	BIT(14)
+#define STM32H7_SPI_CFG1_TXDMAEN	BIT(15)
+#define STM32H7_SPI_CFG1_MBR_SHIFT	28
+#define STM32H7_SPI_CFG1_MBR		GENMASK(30, 28)
+#define STM32H7_SPI_CFG1_MBR_MIN	0
+#define STM32H7_SPI_CFG1_MBR_MAX	(GENMASK(30, 28) >> 28)
+
+/* STM32H7_SPI_CFG2 bit fields */
+#define STM32H7_SPI_CFG2_MIDI_SHIFT	4
+#define STM32H7_SPI_CFG2_MIDI		GENMASK(7, 4)
+#define STM32H7_SPI_CFG2_COMM_SHIFT	17
+#define STM32H7_SPI_CFG2_COMM		GENMASK(18, 17)
+#define STM32H7_SPI_CFG2_SP_SHIFT	19
+#define STM32H7_SPI_CFG2_SP		GENMASK(21, 19)
+#define STM32H7_SPI_CFG2_MASTER		BIT(22)
+#define STM32H7_SPI_CFG2_LSBFRST	BIT(23)
+#define STM32H7_SPI_CFG2_CPHA		BIT(24)
+#define STM32H7_SPI_CFG2_CPOL		BIT(25)
+#define STM32H7_SPI_CFG2_SSM		BIT(26)
+#define STM32H7_SPI_CFG2_AFCNTR		BIT(31)
+
+/* STM32H7_SPI_IER bit fields */
+#define STM32H7_SPI_IER_RXPIE		BIT(0)
+#define STM32H7_SPI_IER_TXPIE		BIT(1)
+#define STM32H7_SPI_IER_DXPIE		BIT(2)
+#define STM32H7_SPI_IER_EOTIE		BIT(3)
+#define STM32H7_SPI_IER_TXTFIE		BIT(4)
+#define STM32H7_SPI_IER_OVRIE		BIT(6)
+#define STM32H7_SPI_IER_MODFIE		BIT(9)
+#define STM32H7_SPI_IER_ALL		GENMASK(10, 0)
+
+/* STM32H7_SPI_SR bit fields */
+#define STM32H7_SPI_SR_RXP		BIT(0)
+#define STM32H7_SPI_SR_TXP		BIT(1)
+#define STM32H7_SPI_SR_EOT		BIT(3)
+#define STM32H7_SPI_SR_OVR		BIT(6)
+#define STM32H7_SPI_SR_MODF		BIT(9)
+#define STM32H7_SPI_SR_SUSP		BIT(11)
+#define STM32H7_SPI_SR_RXPLVL_SHIFT	13
+#define STM32H7_SPI_SR_RXPLVL		GENMASK(14, 13)
+#define STM32H7_SPI_SR_RXWNE		BIT(15)
+
+/* STM32H7_SPI_IFCR bit fields */
+#define STM32H7_SPI_IFCR_ALL		GENMASK(11, 3)
+
+/* STM32H7_SPI_I2SCFGR bit fields */
+#define STM32H7_SPI_I2SCFGR_I2SMOD	BIT(0)
+
+/* STM32H7 SPI Master Baud Rate min/max divisor */
+#define STM32H7_SPI_MBR_DIV_MIN		(2 << STM32H7_SPI_CFG1_MBR_MIN)
+#define STM32H7_SPI_MBR_DIV_MAX		(2 << STM32H7_SPI_CFG1_MBR_MAX)
+
+/* STM32H7 SPI Communication mode */
+#define STM32H7_SPI_FULL_DUPLEX		0
+#define STM32H7_SPI_SIMPLEX_TX		1
+#define STM32H7_SPI_SIMPLEX_RX		2
+#define STM32H7_SPI_HALF_DUPLEX		3
+
+#define STM32H7_SPI_1HZ_NS		1000000000
 
 /**
- * struct stm32_spi - private data of the SPI controller
+ * struct stm32h7_spi - private data of the SPI controller
  * @dev: driver model representation of the controller
  * @master: controller master interface
  * @base: virtual memory area
@@ -148,7 +148,7 @@
  * @dma_rx: dma channel for RX transfer
  * @phys_addr: SPI registers physical base address
  */
-struct stm32_spi {
+struct stm32h7_spi {
 	struct device *dev;
 	struct spi_master *master;
 	void __iomem *base;
@@ -176,37 +176,37 @@ struct stm32_spi {
 	dma_addr_t phys_addr;
 };
 
-static inline void stm32_spi_set_bits(struct stm32_spi *spi,
-				      u32 offset, u32 bits)
+static inline void stm32h7_spi_set_bits(struct stm32h7_spi *spi,
+					u32 offset, u32 bits)
 {
 	writel_relaxed(readl_relaxed(spi->base + offset) | bits,
 		       spi->base + offset);
 }
 
-static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
-				      u32 offset, u32 bits)
+static inline void stm32h7_spi_clr_bits(struct stm32h7_spi *spi,
+					u32 offset, u32 bits)
 {
 	writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
 		       spi->base + offset);
 }
 
 /**
- * stm32_spi_get_fifo_size - Return fifo size
+ * stm32h7_spi_get_fifo_size - Return fifo size
  * @spi: pointer to the spi controller data structure
  */
-static int stm32_spi_get_fifo_size(struct stm32_spi *spi)
+static int stm32h7_spi_get_fifo_size(struct stm32h7_spi *spi)
 {
 	unsigned long flags;
 	u32 count = 0;
 
 	spin_lock_irqsave(&spi->lock, flags);
 
-	stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
+	stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
 
-	while (readl_relaxed(spi->base + STM32_SPI_SR) & SPI_SR_TXP)
-		writeb_relaxed(++count, spi->base + STM32_SPI_TXDR);
+	while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
+		writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
 
-	stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
+	stm32h7_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
 
 	spin_unlock_irqrestore(&spi->lock, flags);
 
@@ -216,10 +216,10 @@ static int stm32_spi_get_fifo_size(struct stm32_spi *spi)
 }
 
 /**
- * stm32_spi_get_bpw_mask - Return bits per word mask
+ * stm32h7_spi_get_bpw_mask - Return bits per word mask
  * @spi: pointer to the spi controller data structure
  */
-static int stm32_spi_get_bpw_mask(struct stm32_spi *spi)
+static int stm32h7_spi_get_bpw_mask(struct stm32h7_spi *spi)
 {
 	unsigned long flags;
 	u32 cfg1, max_bpw;
@@ -230,10 +230,11 @@ static int stm32_spi_get_bpw_mask(struct stm32_spi *spi)
 	 * The most significant bit at DSIZE bit field is reserved when the
 	 * maximum data size of periperal instances is limited to 16-bit
 	 */
-	stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_DSIZE);
+	stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
 
-	cfg1 = readl_relaxed(spi->base + STM32_SPI_CFG1);
-	max_bpw = (cfg1 & SPI_CFG1_DSIZE) >> SPI_CFG1_DSIZE_SHIFT;
+	cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
+	max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >>
+		  STM32H7_SPI_CFG1_DSIZE_SHIFT;
 	max_bpw += 1;
 
 	spin_unlock_irqrestore(&spi->lock, flags);
@@ -244,13 +245,13 @@ static int stm32_spi_get_bpw_mask(struct stm32_spi *spi)
 }
 
 /**
- * stm32_spi_prepare_mbr - Determine SPI_CFG1.MBR value
+ * stm32h7_spi_prepare_mbr - Determine STM32H7_SPI_CFG1.MBR value
  * @spi: pointer to the spi controller data structure
  * @speed_hz: requested speed
  *
- * Return SPI_CFG1.MBR value in case of success or -EINVAL
+ * Return STM32H7_SPI_CFG1.MBR value in case of success or -EINVAL
  */
-static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz)
+static int stm32h7_spi_prepare_mbr(struct stm32h7_spi *spi, u32 speed_hz)
 {
 	u32 div, mbrdiv;
 
@@ -263,8 +264,8 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz)
 	 * no need to check it there.
 	 * However, we need to ensure the following calculations.
 	 */
-	if (div < SPI_MBR_DIV_MIN ||
-	    div > SPI_MBR_DIV_MAX)
+	if (div < STM32H7_SPI_MBR_DIV_MIN ||
+	    div > STM32H7_SPI_MBR_DIV_MAX)
 		return -EINVAL;
 
 	/* Determine the first power of 2 greater than or equal to div */
@@ -279,10 +280,10 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz)
 }
 
 /**
- * stm32_spi_prepare_fthlv - Determine FIFO threshold level
+ * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
  * @spi: pointer to the spi controller data structure
  */
-static u32 stm32_spi_prepare_fthlv(struct stm32_spi *spi)
+static u32 stm32h7_spi_prepare_fthlv(struct stm32h7_spi *spi)
 {
 	u32 fthlv, half_fifo;
 
@@ -306,32 +307,33 @@ static u32 stm32_spi_prepare_fthlv(struct stm32_spi *spi)
 }
 
 /**
- * stm32_spi_write_txfifo - Write bytes in Transmit Data Register
+ * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
  * @spi: pointer to the spi controller data structure
  *
  * Read from tx_buf depends on remaining bytes to avoid to read beyond
  * tx_buf end.
  */
-static void stm32_spi_write_txfifo(struct stm32_spi *spi)
+static void stm32h7_spi_write_txfifo(struct stm32h7_spi *spi)
 {
 	while ((spi->tx_len > 0) &&
-	       (readl_relaxed(spi->base + STM32_SPI_SR) & SPI_SR_TXP)) {
+	       (readl_relaxed(spi->base + STM32H7_SPI_SR) &
+		STM32H7_SPI_SR_TXP)) {
 		u32 offs = spi->cur_xferlen - spi->tx_len;
 
 		if (spi->tx_len >= sizeof(u32)) {
 			const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
 
-			writel_relaxed(*tx_buf32, spi->base + STM32_SPI_TXDR);
+			writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
 			spi->tx_len -= sizeof(u32);
 		} else if (spi->tx_len >= sizeof(u16)) {
 			const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
 
-			writew_relaxed(*tx_buf16, spi->base + STM32_SPI_TXDR);
+			writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
 			spi->tx_len -= sizeof(u16);
 		} else {
 			const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
 
-			writeb_relaxed(*tx_buf8, spi->base + STM32_SPI_TXDR);
+			writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
 			spi->tx_len -= sizeof(u8);
 		}
 	}
@@ -340,43 +342,45 @@ static void stm32_spi_write_txfifo(struct stm32_spi *spi)
 }
 
 /**
- * stm32_spi_read_rxfifo - Read bytes in Receive Data Register
+ * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
  * @spi: pointer to the spi controller data structure
  *
  * Write in rx_buf depends on remaining bytes to avoid to write beyond
  * rx_buf end.
  */
-static void stm32_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
+static void stm32h7_spi_read_rxfifo(struct stm32h7_spi *spi, bool flush)
 {
-	u32 sr = readl_relaxed(spi->base + STM32_SPI_SR);
-	u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
+	u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
+	u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
+		     STM32H7_SPI_SR_RXPLVL_SHIFT;
 
 	while ((spi->rx_len > 0) &&
-	       ((sr & SPI_SR_RXP) ||
-		(flush && ((sr & SPI_SR_RXWNE) || (rxplvl > 0))))) {
+	       ((sr & STM32H7_SPI_SR_RXP) ||
+		(flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
 		u32 offs = spi->cur_xferlen - spi->rx_len;
 
 		if ((spi->rx_len >= sizeof(u32)) ||
-		    (flush && (sr & SPI_SR_RXWNE))) {
+		    (flush && (sr & STM32H7_SPI_SR_RXWNE))) {
 			u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
 
-			*rx_buf32 = readl_relaxed(spi->base + STM32_SPI_RXDR);
+			*rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
 			spi->rx_len -= sizeof(u32);
 		} else if ((spi->rx_len >= sizeof(u16)) ||
 			   (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) {
 			u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
 
-			*rx_buf16 = readw_relaxed(spi->base + STM32_SPI_RXDR);
+			*rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
 			spi->rx_len -= sizeof(u16);
 		} else {
 			u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
 
-			*rx_buf8 = readb_relaxed(spi->base + STM32_SPI_RXDR);
+			*rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
 			spi->rx_len -= sizeof(u8);
 		}
 
-		sr = readl_relaxed(spi->base + STM32_SPI_SR);
-		rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
+		sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
+		rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
+			 STM32H7_SPI_SR_RXPLVL_SHIFT;
 	}
 
 	dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
@@ -384,28 +388,28 @@ static void stm32_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
 }
 
 /**
- * stm32_spi_enable - Enable SPI controller
+ * stm32h7_spi_enable - Enable SPI controller
  * @spi: pointer to the spi controller data structure
  *
  * SPI data transfer is enabled but spi_ker_ck is idle.
- * SPI_CFG1 and SPI_CFG2 are now write protected.
+ * STM32H7_SPI_CFG1 and STM32H7_SPI_CFG2 are now write protected.
  */
-static void stm32_spi_enable(struct stm32_spi *spi)
+static void stm32h7_spi_enable(struct stm32h7_spi *spi)
 {
 	dev_dbg(spi->dev, "enable controller\n");
 
-	stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
+	stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
 }
 
 /**
- * stm32_spi_disable - Disable SPI controller
+ * stm32h7_spi_disable - Disable SPI controller
  * @spi: pointer to the spi controller data structure
  *
  * RX-Fifo is flushed when SPI controller is disabled. To prevent any data
- * loss, use stm32_spi_read_rxfifo(flush) to read the remaining bytes in
+ * loss, use stm32h7_spi_read_rxfifo(flush) to read the remaining bytes in
  * RX-Fifo.
  */
-static void stm32_spi_disable(struct stm32_spi *spi)
+static void stm32h7_spi_disable(struct stm32h7_spi *spi)
 {
 	unsigned long flags;
 	u32 cr1, sr;
@@ -414,23 +418,23 @@ static void stm32_spi_disable(struct stm32_spi *spi)
 
 	spin_lock_irqsave(&spi->lock, flags);
 
-	cr1 = readl_relaxed(spi->base + STM32_SPI_CR1);
+	cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
 
-	if (!(cr1 & SPI_CR1_SPE)) {
+	if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
 		spin_unlock_irqrestore(&spi->lock, flags);
 		return;
 	}
 
 	/* Wait on EOT or suspend the flow */
-	if (readl_relaxed_poll_timeout_atomic(spi->base + STM32_SPI_SR,
-					      sr, !(sr & SPI_SR_EOT),
+	if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR,
+					      sr, !(sr & STM32H7_SPI_SR_EOT),
 					      10, 100000) < 0) {
-		if (cr1 & SPI_CR1_CSTART) {
-			writel_relaxed(cr1 | SPI_CR1_CSUSP,
-				       spi->base + STM32_SPI_CR1);
+		if (cr1 & STM32H7_SPI_CR1_CSTART) {
+			writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP,
+				       spi->base + STM32H7_SPI_CR1);
 			if (readl_relaxed_poll_timeout_atomic(
-						spi->base + STM32_SPI_SR,
-						sr, !(sr & SPI_SR_SUSP),
+						spi->base + STM32H7_SPI_SR,
+						sr, !(sr & STM32H7_SPI_SR_SUSP),
 						10, 100000) < 0)
 				dev_warn(spi->dev,
 					 "Suspend request timeout\n");
@@ -438,35 +442,35 @@ static void stm32_spi_disable(struct stm32_spi *spi)
 	}
 
 	if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0))
-		stm32_spi_read_rxfifo(spi, true);
+		stm32h7_spi_read_rxfifo(spi, true);
 
 	if (spi->cur_usedma && spi->tx_buf)
 		dmaengine_terminate_all(spi->dma_tx);
 	if (spi->cur_usedma && spi->rx_buf)
 		dmaengine_terminate_all(spi->dma_rx);
 
-	stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
+	stm32h7_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
 
-	stm32_spi_clr_bits(spi, STM32_SPI_CFG1, SPI_CFG1_TXDMAEN |
-						SPI_CFG1_RXDMAEN);
+	stm32h7_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
+						    STM32H7_SPI_CFG1_RXDMAEN);
 
 	/* Disable interrupts and clear status flags */
-	writel_relaxed(0, spi->base + STM32_SPI_IER);
-	writel_relaxed(SPI_IFCR_ALL, spi->base + STM32_SPI_IFCR);
+	writel_relaxed(0, spi->base + STM32H7_SPI_IER);
+	writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
 
 	spin_unlock_irqrestore(&spi->lock, flags);
 }
 
 /**
- * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
+ * stm32h7_spi_can_dma - Determine if the transfer is eligible for DMA use
  *
  * If the current transfer size is greater than fifo size, use DMA.
  */
-static bool stm32_spi_can_dma(struct spi_master *master,
-			      struct spi_device *spi_dev,
-			      struct spi_transfer *transfer)
+static bool stm32h7_spi_can_dma(struct spi_master *master,
+				struct spi_device *spi_dev,
+				struct spi_transfer *transfer)
 {
-	struct stm32_spi *spi = spi_master_get_devdata(master);
+	struct stm32h7_spi *spi = spi_master_get_devdata(master);
 
 	dev_dbg(spi->dev, "%s: %s\n", __func__,
 		(transfer->len > spi->fifo_size) ? "true" : "false");
@@ -475,33 +479,33 @@ static bool stm32_spi_can_dma(struct spi_master *master,
 }
 
 /**
- * stm32_spi_irq - Interrupt handler for SPI controller events
+ * stm32h7_spi_irq - Interrupt handler for SPI controller events
  * @irq: interrupt line
  * @dev_id: SPI controller master interface
  */
-static irqreturn_t stm32_spi_irq(int irq, void *dev_id)
+static irqreturn_t stm32h7_spi_irq(int irq, void *dev_id)
 {
 	struct spi_master *master = dev_id;
-	struct stm32_spi *spi = spi_master_get_devdata(master);
+	struct stm32h7_spi *spi = spi_master_get_devdata(master);
 	u32 sr, ier, mask;
 	unsigned long flags;
 	bool end = false;
 
 	spin_lock_irqsave(&spi->lock, flags);
 
-	sr = readl_relaxed(spi->base + STM32_SPI_SR);
-	ier = readl_relaxed(spi->base + STM32_SPI_IER);
+	sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
+	ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
 
 	mask = ier;
 	/* EOTIE is triggered on EOT, SUSP and TXC events. */
-	mask |= SPI_SR_SUSP;
+	mask |= STM32H7_SPI_SR_SUSP;
 	/*
 	 * When TXTF is set, DXPIE and TXPIE are cleared. So in case of
 	 * Full-Duplex, need to poll RXP event to know if there are remaining
 	 * data, before disabling SPI.
 	 */
 	if (spi->rx_buf && !spi->cur_usedma)
-		mask |= SPI_SR_RXP;
+		mask |= STM32H7_SPI_SR_RXP;
 
 	if (!(sr & mask)) {
 		dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
@@ -510,10 +514,10 @@ static irqreturn_t stm32_spi_irq(int irq, void *dev_id)
 		return IRQ_NONE;
 	}
 
-	if (sr & SPI_SR_SUSP) {
+	if (sr & STM32H7_SPI_SR_SUSP) {
 		dev_warn(spi->dev, "Communication suspended\n");
 		if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
-			stm32_spi_read_rxfifo(spi, false);
+			stm32h7_spi_read_rxfifo(spi, false);
 		/*
 		 * If communication is suspended while using DMA, it means
 		 * that something went wrong, so stop the current transfer
@@ -522,15 +526,15 @@ static irqreturn_t stm32_spi_irq(int irq, void *dev_id)
 			end = true;
 	}
 
-	if (sr & SPI_SR_MODF) {
+	if (sr & STM32H7_SPI_SR_MODF) {
 		dev_warn(spi->dev, "Mode fault: transfer aborted\n");
 		end = true;
 	}
 
-	if (sr & SPI_SR_OVR) {
+	if (sr & STM32H7_SPI_SR_OVR) {
 		dev_warn(spi->dev, "Overrun: received value discarded\n");
 		if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
-			stm32_spi_read_rxfifo(spi, false);
+			stm32h7_spi_read_rxfifo(spi, false);
 		/*
 		 * If overrun is detected while using DMA, it means that
 		 * something went wrong, so stop the current transfer
@@ -539,36 +543,36 @@ static irqreturn_t stm32_spi_irq(int irq, void *dev_id)
 			end = true;
 	}
 
-	if (sr & SPI_SR_EOT) {
+	if (sr & STM32H7_SPI_SR_EOT) {
 		if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
-			stm32_spi_read_rxfifo(spi, true);
+			stm32h7_spi_read_rxfifo(spi, true);
 		end = true;
 	}
 
-	if (sr & SPI_SR_TXP)
+	if (sr & STM32H7_SPI_SR_TXP)
 		if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
-			stm32_spi_write_txfifo(spi);
+			stm32h7_spi_write_txfifo(spi);
 
-	if (sr & SPI_SR_RXP)
+	if (sr & STM32H7_SPI_SR_RXP)
 		if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
-			stm32_spi_read_rxfifo(spi, false);
+			stm32h7_spi_read_rxfifo(spi, false);
 
-	writel_relaxed(mask, spi->base + STM32_SPI_IFCR);
+	writel_relaxed(mask, spi->base + STM32H7_SPI_IFCR);
 
 	spin_unlock_irqrestore(&spi->lock, flags);
 
 	if (end) {
 		spi_finalize_current_transfer(master);
-		stm32_spi_disable(spi);
+		stm32h7_spi_disable(spi);
 	}
 
 	return IRQ_HANDLED;
 }
 
 /**
- * stm32_spi_setup - setup device chip select
+ * stm32h7_spi_setup - setup device chip select
  */
-static int stm32_spi_setup(struct spi_device *spi_dev)
+static int stm32h7_spi_setup(struct spi_device *spi_dev)
 {
 	int ret = 0;
 
@@ -589,12 +593,12 @@ static int stm32_spi_setup(struct spi_device *spi_dev)
 }
 
 /**
- * stm32_spi_prepare_msg - set up the controller to transfer a single message
+ * stm32h7_spi_prepare_msg - set up the controller to transfer a single message
  */
-static int stm32_spi_prepare_msg(struct spi_master *master,
-				 struct spi_message *msg)
+static int stm32h7_spi_prepare_msg(struct spi_master *master,
+				   struct spi_message *msg)
 {
-	struct stm32_spi *spi = spi_master_get_devdata(master);
+	struct stm32h7_spi *spi = spi_master_get_devdata(master);
 	struct spi_device *spi_dev = msg->spi;
 	struct device_node *np = spi_dev->dev.of_node;
 	unsigned long flags;
@@ -606,19 +610,19 @@ static int stm32_spi_prepare_msg(struct spi_master *master,
 		dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
 
 	if (spi_dev->mode & SPI_CPOL)
-		cfg2_setb |= SPI_CFG2_CPOL;
+		cfg2_setb |= STM32H7_SPI_CFG2_CPOL;
 	else
-		cfg2_clrb |= SPI_CFG2_CPOL;
+		cfg2_clrb |= STM32H7_SPI_CFG2_CPOL;
 
 	if (spi_dev->mode & SPI_CPHA)
-		cfg2_setb |= SPI_CFG2_CPHA;
+		cfg2_setb |= STM32H7_SPI_CFG2_CPHA;
 	else
-		cfg2_clrb |= SPI_CFG2_CPHA;
+		cfg2_clrb |= STM32H7_SPI_CFG2_CPHA;
 
 	if (spi_dev->mode & SPI_LSB_FIRST)
-		cfg2_setb |= SPI_CFG2_LSBFRST;
+		cfg2_setb |= STM32H7_SPI_CFG2_LSBFRST;
 	else
-		cfg2_clrb |= SPI_CFG2_LSBFRST;
+		cfg2_clrb |= STM32H7_SPI_CFG2_LSBFRST;
 
 	dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
 		spi_dev->mode & SPI_CPOL,
@@ -630,9 +634,9 @@ static int stm32_spi_prepare_msg(struct spi_master *master,
 
 	if (cfg2_clrb || cfg2_setb)
 		writel_relaxed(
-			(readl_relaxed(spi->base + STM32_SPI_CFG2) &
+			(readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
 				~cfg2_clrb) | cfg2_setb,
-			       spi->base + STM32_SPI_CFG2);
+			       spi->base + STM32H7_SPI_CFG2);
 
 	spin_unlock_irqrestore(&spi->lock, flags);
 
@@ -640,36 +644,36 @@ static int stm32_spi_prepare_msg(struct spi_master *master,
 }
 
 /**
- * stm32_spi_dma_cb - dma callback
+ * stm32h7_spi_dma_cb - dma callback
  *
  * DMA callback is called when the transfer is complete or when an error
  * occurs. If the transfer is complete, EOT flag is raised.
  */
-static void stm32_spi_dma_cb(void *data)
+static void stm32h7_spi_dma_cb(void *data)
 {
-	struct stm32_spi *spi = data;
+	struct stm32h7_spi *spi = data;
 	unsigned long flags;
 	u32 sr;
 
 	spin_lock_irqsave(&spi->lock, flags);
 
-	sr = readl_relaxed(spi->base + STM32_SPI_SR);
+	sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
 
 	spin_unlock_irqrestore(&spi->lock, flags);
 
-	if (!(sr & SPI_SR_EOT))
+	if (!(sr & STM32H7_SPI_SR_EOT))
 		dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr);
 
 	/* Now wait for EOT, or SUSP or OVR in case of error */
 }
 
 /**
- * stm32_spi_dma_config - configure dma slave channel depending on current
- *			  transfer bits_per_word.
+ * stm32h7_spi_dma_config - configure dma slave channel depending on current
+ *			    transfer bits_per_word.
  */
-static void stm32_spi_dma_config(struct stm32_spi *spi,
-				 struct dma_slave_config *dma_conf,
-				 enum dma_transfer_direction dir)
+static void stm32h7_spi_dma_config(struct stm32h7_spi *spi,
+				   struct dma_slave_config *dma_conf,
+				   enum dma_transfer_direction dir)
 {
 	enum dma_slave_buswidth buswidth;
 	u32 maxburst;
@@ -690,14 +694,14 @@ static void stm32_spi_dma_config(struct stm32_spi *spi,
 	memset(dma_conf, 0, sizeof(struct dma_slave_config));
 	dma_conf->direction = dir;
 	if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
-		dma_conf->src_addr = spi->phys_addr + STM32_SPI_RXDR;
+		dma_conf->src_addr = spi->phys_addr + STM32H7_SPI_RXDR;
 		dma_conf->src_addr_width = buswidth;
 		dma_conf->src_maxburst = maxburst;
 
 		dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
 			buswidth, maxburst);
 	} else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
-		dma_conf->dst_addr = spi->phys_addr + STM32_SPI_TXDR;
+		dma_conf->dst_addr = spi->phys_addr + STM32H7_SPI_TXDR;
 		dma_conf->dst_addr_width = buswidth;
 		dma_conf->dst_maxburst = maxburst;
 
@@ -707,39 +711,40 @@ static void stm32_spi_dma_config(struct stm32_spi *spi,
 }
 
 /**
- * stm32_spi_transfer_one_irq - transfer a single spi_transfer using
- *				interrupts
+ * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
+ *				  interrupts
  *
  * It must returns 0 if the transfer is finished or 1 if the transfer is still
  * in progress.
  */
-static int stm32_spi_transfer_one_irq(struct stm32_spi *spi)
+static int stm32h7_spi_transfer_one_irq(struct stm32h7_spi *spi)
 {
 	unsigned long flags;
 	u32 ier = 0;
 
 	/* Enable the interrupts relative to the current communication mode */
 	if (spi->tx_buf && spi->rx_buf)	/* Full Duplex */
-		ier |= SPI_IER_DXPIE;
+		ier |= STM32H7_SPI_IER_DXPIE;
 	else if (spi->tx_buf)		/* Half-Duplex TX dir or Simplex TX */
-		ier |= SPI_IER_TXPIE;
+		ier |= STM32H7_SPI_IER_TXPIE;
 	else if (spi->rx_buf)		/* Half-Duplex RX dir or Simplex RX */
-		ier |= SPI_IER_RXPIE;
+		ier |= STM32H7_SPI_IER_RXPIE;
 
 	/* Enable the interrupts relative to the end of transfer */
-	ier |= SPI_IER_EOTIE | SPI_IER_TXTFIE |	SPI_IER_OVRIE |	SPI_IER_MODFIE;
+	ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
+	       STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
 
 	spin_lock_irqsave(&spi->lock, flags);
 
-	stm32_spi_enable(spi);
+	stm32h7_spi_enable(spi);
 
 	/* Be sure to have data in fifo before starting data transfer */
 	if (spi->tx_buf)
-		stm32_spi_write_txfifo(spi);
+		stm32h7_spi_write_txfifo(spi);
 
-	stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_CSTART);
+	stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
 
-	writel_relaxed(ier, spi->base + STM32_SPI_IER);
+	writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
 
 	spin_unlock_irqrestore(&spi->lock, flags);
 
@@ -747,13 +752,13 @@ static int stm32_spi_transfer_one_irq(struct stm32_spi *spi)
 }
 
 /**
- * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
+ * stm32h7_spi_transfer_one_dma - transfer a single spi_transfer using DMA
  *
  * It must returns 0 if the transfer is finished or 1 if the transfer is still
  * in progress.
  */
-static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
-				      struct spi_transfer *xfer)
+static int stm32h7_spi_transfer_one_dma(struct stm32h7_spi *spi,
+					struct spi_transfer *xfer)
 {
 	struct dma_slave_config tx_dma_conf, rx_dma_conf;
 	struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
@@ -764,11 +769,12 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
 
 	rx_dma_desc = NULL;
 	if (spi->rx_buf) {
-		stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
+		stm32h7_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
 		dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
 
 		/* Enable Rx DMA request */
-		stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_RXDMAEN);
+		stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG1,
+				   STM32H7_SPI_CFG1_RXDMAEN);
 
 		rx_dma_desc = dmaengine_prep_slave_sg(
 					spi->dma_rx, xfer->rx_sg.sgl,
@@ -779,7 +785,7 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
 
 	tx_dma_desc = NULL;
 	if (spi->tx_buf) {
-		stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
+		stm32h7_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
 		dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
 
 		tx_dma_desc = dmaengine_prep_slave_sg(
@@ -794,7 +800,7 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
 		goto dma_desc_error;
 
 	if (rx_dma_desc) {
-		rx_dma_desc->callback = stm32_spi_dma_cb;
+		rx_dma_desc->callback = stm32h7_spi_dma_cb;
 		rx_dma_desc->callback_param = spi;
 
 		if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
@@ -806,8 +812,8 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
 	}
 
 	if (tx_dma_desc) {
-		if (spi->cur_comm == SPI_SIMPLEX_TX) {
-			tx_dma_desc->callback = stm32_spi_dma_cb;
+		if (spi->cur_comm == STM32H7_SPI_SIMPLEX_TX) {
+			tx_dma_desc->callback = stm32h7_spi_dma_cb;
 			tx_dma_desc->callback_param = spi;
 		}
 
@@ -819,16 +825,18 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
 		dma_async_issue_pending(spi->dma_tx);
 
 		/* Enable Tx DMA request */
-		stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_TXDMAEN);
+		stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG1,
+				     STM32H7_SPI_CFG1_TXDMAEN);
 	}
 
 	/* Enable the interrupts relative to the end of transfer */
-	ier |= SPI_IER_EOTIE | SPI_IER_TXTFIE |	SPI_IER_OVRIE |	SPI_IER_MODFIE;
-	writel_relaxed(ier, spi->base + STM32_SPI_IER);
+	ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
+	       STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
+	writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
 
-	stm32_spi_enable(spi);
+	stm32h7_spi_enable(spi);
 
-	stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_CSTART);
+	stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
 
 	spin_unlock_irqrestore(&spi->lock, flags);
 
@@ -839,23 +847,23 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
 		dmaengine_terminate_all(spi->dma_rx);
 
 dma_desc_error:
-	stm32_spi_clr_bits(spi, STM32_SPI_CFG1, SPI_CFG1_RXDMAEN);
+	stm32h7_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN);
 
 	spin_unlock_irqrestore(&spi->lock, flags);
 
 	dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
 
-	return stm32_spi_transfer_one_irq(spi);
+	return stm32h7_spi_transfer_one_irq(spi);
 }
 
 /**
- * stm32_spi_transfer_one_setup - common setup to transfer a single
- *				  spi_transfer either using DMA or
- *				  interrupts.
+ * stm32h7_spi_transfer_one_setup - common setup to transfer a single
+ *				    spi_transfer either using DMA or
+ *				    interrupts.
  */
-static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
-					struct spi_device *spi_dev,
-					struct spi_transfer *transfer)
+static int stm32h7_spi_transfer_one_setup(struct stm32h7_spi *spi,
+					  struct spi_device *spi_dev,
+					  struct spi_transfer *transfer)
 {
 	unsigned long flags;
 	u32 cfg1_clrb = 0, cfg1_setb = 0, cfg2_clrb = 0, cfg2_setb = 0;
@@ -870,21 +878,23 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
 		spi->cur_bpw = transfer->bits_per_word;
 		bpw = spi->cur_bpw - 1;
 
-		cfg1_clrb |= SPI_CFG1_DSIZE;
-		cfg1_setb |= (bpw << SPI_CFG1_DSIZE_SHIFT) & SPI_CFG1_DSIZE;
+		cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
+		cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
+			     STM32H7_SPI_CFG1_DSIZE;
 
-		spi->cur_fthlv = stm32_spi_prepare_fthlv(spi);
+		spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi);
 		fthlv = spi->cur_fthlv - 1;
 
-		cfg1_clrb |= SPI_CFG1_FTHLV;
-		cfg1_setb |= (fthlv << SPI_CFG1_FTHLV_SHIFT) & SPI_CFG1_FTHLV;
+		cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
+		cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
+			     STM32H7_SPI_CFG1_FTHLV;
 	}
 
 	if (spi->cur_speed != transfer->speed_hz) {
 		int mbr;
 
 		/* Update spi->cur_speed with real clock speed */
-		mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz);
+		mbr = stm32h7_spi_prepare_mbr(spi, transfer->speed_hz);
 		if (mbr < 0) {
 			ret = mbr;
 			goto out;
@@ -892,16 +902,17 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
 
 		transfer->speed_hz = spi->cur_speed;
 
-		cfg1_clrb |= SPI_CFG1_MBR;
-		cfg1_setb |= ((u32)mbr << SPI_CFG1_MBR_SHIFT) & SPI_CFG1_MBR;
+		cfg1_clrb |= STM32H7_SPI_CFG1_MBR;
+		cfg1_setb |= ((u32)mbr << STM32H7_SPI_CFG1_MBR_SHIFT) &
+			     STM32H7_SPI_CFG1_MBR;
 	}
 
 	if (cfg1_clrb || cfg1_setb)
-		writel_relaxed((readl_relaxed(spi->base + STM32_SPI_CFG1) &
+		writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
 				~cfg1_clrb) | cfg1_setb,
-			       spi->base + STM32_SPI_CFG1);
+			       spi->base + STM32H7_SPI_CFG1);
 
-	mode = SPI_FULL_DUPLEX;
+	mode = STM32H7_SPI_FULL_DUPLEX;
 	if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
 		/*
 		 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
@@ -909,40 +920,46 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
 		 * on the valid buffer, we can determine the direction of the
 		 * transfer.
 		 */
-		mode = SPI_HALF_DUPLEX;
+		mode = STM32H7_SPI_HALF_DUPLEX;
 		if (!transfer->tx_buf)
-			stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_HDDIR);
+			stm32h7_spi_clr_bits(spi, STM32H7_SPI_CR1,
+					     STM32H7_SPI_CR1_HDDIR);
 		else if (!transfer->rx_buf)
-			stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_HDDIR);
+			stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1,
+					     STM32H7_SPI_CR1_HDDIR);
 	} else {
 		if (!transfer->tx_buf)
-			mode = SPI_SIMPLEX_RX;
+			mode = STM32H7_SPI_SIMPLEX_RX;
 		else if (!transfer->rx_buf)
-			mode = SPI_SIMPLEX_TX;
+			mode = STM32H7_SPI_SIMPLEX_TX;
 	}
 	if (spi->cur_comm != mode) {
 		spi->cur_comm = mode;
 
-		cfg2_clrb |= SPI_CFG2_COMM;
-		cfg2_setb |= (mode << SPI_CFG2_COMM_SHIFT) & SPI_CFG2_COMM;
+		cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
+		cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) &
+			     STM32H7_SPI_CFG2_COMM;
 	}
 
-	cfg2_clrb |= SPI_CFG2_MIDI;
+	cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
 	if ((transfer->len > 1) && (spi->cur_midi > 0)) {
-		u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
+		u32 sck_period_ns = DIV_ROUND_UP(STM32H7_SPI_1HZ_NS,
+						 spi->cur_speed);
 		u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
-			       (u32)SPI_CFG2_MIDI >> SPI_CFG2_MIDI_SHIFT);
+			       (u32)STM32H7_SPI_CFG2_MIDI >>
+			       STM32H7_SPI_CFG2_MIDI_SHIFT);
 
 		dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
 			sck_period_ns, midi, midi * sck_period_ns);
 
-		cfg2_setb |= (midi << SPI_CFG2_MIDI_SHIFT) & SPI_CFG2_MIDI;
+		cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) &
+			     STM32H7_SPI_CFG2_MIDI;
 	}
 
 	if (cfg2_clrb || cfg2_setb)
-		writel_relaxed((readl_relaxed(spi->base + STM32_SPI_CFG2) &
+		writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
 				~cfg2_clrb) | cfg2_setb,
-			       spi->base + STM32_SPI_CFG2);
+			       spi->base + STM32H7_SPI_CFG2);
 
 	if (spi->cur_bpw <= 8)
 		nb_words = transfer->len;
@@ -950,10 +967,10 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
 		nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
 	else
 		nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
-	nb_words <<= SPI_CR2_TSIZE_SHIFT;
+	nb_words <<= STM32H7_SPI_CR2_TSIZE_SHIFT;
 
-	if (nb_words <= SPI_CR2_TSIZE) {
-		writel_relaxed(nb_words, spi->base + STM32_SPI_CR2);
+	if (nb_words <= STM32H7_SPI_CR2_TSIZE) {
+		writel_relaxed(nb_words, spi->base + STM32H7_SPI_CR2);
 	} else {
 		ret = -EMSGSIZE;
 		goto out;
@@ -979,16 +996,16 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
 }
 
 /**
- * stm32_spi_transfer_one - transfer a single spi_transfer
+ * stm32h7_spi_transfer_one - transfer a single spi_transfer
  *
  * It must return 0 if the transfer is finished or 1 if the transfer is still
  * in progress.
  */
-static int stm32_spi_transfer_one(struct spi_master *master,
-				  struct spi_device *spi_dev,
-				  struct spi_transfer *transfer)
+static int stm32h7_spi_transfer_one(struct spi_master *master,
+				    struct spi_device *spi_dev,
+				    struct spi_transfer *transfer)
 {
-	struct stm32_spi *spi = spi_master_get_devdata(master);
+	struct stm32h7_spi *spi = spi_master_get_devdata(master);
 	int ret;
 
 	spi->tx_buf = transfer->tx_buf;
@@ -997,58 +1014,59 @@ static int stm32_spi_transfer_one(struct spi_master *master,
 	spi->rx_len = spi->rx_buf ? transfer->len : 0;
 
 	spi->cur_usedma = (master->can_dma &&
-			   stm32_spi_can_dma(master, spi_dev, transfer));
+			   stm32h7_spi_can_dma(master, spi_dev, transfer));
 
-	ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
+	ret = stm32h7_spi_transfer_one_setup(spi, spi_dev, transfer);
 	if (ret) {
 		dev_err(spi->dev, "SPI transfer setup failed\n");
 		return ret;
 	}
 
 	if (spi->cur_usedma)
-		return stm32_spi_transfer_one_dma(spi, transfer);
+		return stm32h7_spi_transfer_one_dma(spi, transfer);
 	else
-		return stm32_spi_transfer_one_irq(spi);
+		return stm32h7_spi_transfer_one_irq(spi);
 }
 
 /**
- * stm32_spi_unprepare_msg - relax the hardware
+ * stm32h7_spi_unprepare_msg - relax the hardware
  *
  * Normally, if TSIZE has been configured, we should relax the hardware at the
  * reception of the EOT interrupt. But in case of error, EOT will not be
  * raised. So the subsystem unprepare_message call allows us to properly
  * complete the transfer from an hardware point of view.
  */
-static int stm32_spi_unprepare_msg(struct spi_master *master,
-				   struct spi_message *msg)
+static int stm32h7_spi_unprepare_msg(struct spi_master *master,
+				     struct spi_message *msg)
 {
-	struct stm32_spi *spi = spi_master_get_devdata(master);
+	struct stm32h7_spi *spi = spi_master_get_devdata(master);
 
-	stm32_spi_disable(spi);
+	stm32h7_spi_disable(spi);
 
 	return 0;
 }
 
 /**
- * stm32_spi_config - Configure SPI controller as SPI master
+ * stm32h7_spi_config - Configure SPI controller as SPI master
  */
-static int stm32_spi_config(struct stm32_spi *spi)
+static int stm32h7_spi_config(struct stm32h7_spi *spi)
 {
 	unsigned long flags;
 
 	spin_lock_irqsave(&spi->lock, flags);
 
 	/* Ensure I2SMOD bit is kept cleared */
-	stm32_spi_clr_bits(spi, STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
+	stm32h7_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
+			     STM32H7_SPI_I2SCFGR_I2SMOD);
 
 	/*
 	 * - SS input value high
 	 * - transmitter half duplex direction
 	 * - automatic communication suspend when RX-Fifo is full
 	 */
-	stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SSI |
-					       SPI_CR1_HDDIR |
-					       SPI_CR1_MASRX);
+	stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI |
+						   STM32H7_SPI_CR1_HDDIR |
+						   STM32H7_SPI_CR1_MASRX);
 
 	/*
 	 * - Set the master mode (default Motorola mode)
@@ -1056,29 +1074,29 @@ static int stm32_spi_config(struct stm32_spi *spi)
 	 *   SS input value is determined by the SSI bit
 	 * - keep control of all associated GPIOs
 	 */
-	stm32_spi_set_bits(spi, STM32_SPI_CFG2, SPI_CFG2_MASTER |
-						SPI_CFG2_SSM |
-						SPI_CFG2_AFCNTR);
+	stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER |
+						    STM32H7_SPI_CFG2_SSM |
+						    STM32H7_SPI_CFG2_AFCNTR);
 
 	spin_unlock_irqrestore(&spi->lock, flags);
 
 	return 0;
 }
 
-static const struct of_device_id stm32_spi_of_match[] = {
+static const struct of_device_id stm32h7_spi_of_match[] = {
 	{ .compatible = "st,stm32h7-spi", },
 	{},
 };
-MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
+MODULE_DEVICE_TABLE(of, stm32h7_spi_of_match);
 
-static int stm32_spi_probe(struct platform_device *pdev)
+static int stm32h7_spi_probe(struct platform_device *pdev)
 {
 	struct spi_master *master;
-	struct stm32_spi *spi;
+	struct stm32h7_spi *spi;
 	struct resource *res;
 	int i, ret;
 
-	master = spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
+	master = spi_alloc_master(&pdev->dev, sizeof(struct stm32h7_spi));
 	if (!master) {
 		dev_err(&pdev->dev, "spi master allocation failed\n");
 		return -ENOMEM;
@@ -1105,7 +1123,7 @@ static int stm32_spi_probe(struct platform_device *pdev)
 		goto err_master_put;
 	}
 	ret = devm_request_threaded_irq(&pdev->dev, spi->irq, NULL,
-					stm32_spi_irq, IRQF_ONESHOT,
+					stm32h7_spi_irq, IRQF_ONESHOT,
 					pdev->name, master);
 	if (ret) {
 		dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
@@ -1139,9 +1157,9 @@ static int stm32_spi_probe(struct platform_device *pdev)
 		reset_control_deassert(spi->rst);
 	}
 
-	spi->fifo_size = stm32_spi_get_fifo_size(spi);
+	spi->fifo_size = stm32h7_spi_get_fifo_size(spi);
 
-	ret = stm32_spi_config(spi);
+	ret = stm32h7_spi_config(spi);
 	if (ret) {
 		dev_err(&pdev->dev, "controller configuration failed: %d\n",
 			ret);
@@ -1153,13 +1171,13 @@ static int stm32_spi_probe(struct platform_device *pdev)
 	master->bus_num = pdev->id;
 	master->mode_bits = SPI_MODE_3 | SPI_CS_HIGH | SPI_LSB_FIRST |
 			    SPI_3WIRE | SPI_LOOP;
-	master->bits_per_word_mask = stm32_spi_get_bpw_mask(spi);
-	master->max_speed_hz = spi->clk_rate / SPI_MBR_DIV_MIN;
-	master->min_speed_hz = spi->clk_rate / SPI_MBR_DIV_MAX;
-	master->setup = stm32_spi_setup;
-	master->prepare_message = stm32_spi_prepare_msg;
-	master->transfer_one = stm32_spi_transfer_one;
-	master->unprepare_message = stm32_spi_unprepare_msg;
+	master->bits_per_word_mask = stm32h7_spi_get_bpw_mask(spi);
+	master->max_speed_hz = spi->clk_rate / STM32H7_SPI_MBR_DIV_MIN;
+	master->min_speed_hz = spi->clk_rate / STM32H7_SPI_MBR_DIV_MAX;
+	master->setup = stm32h7_spi_setup;
+	master->prepare_message = stm32h7_spi_prepare_msg;
+	master->transfer_one = stm32h7_spi_transfer_one;
+	master->unprepare_message = stm32h7_spi_unprepare_msg;
 
 	spi->dma_tx = dma_request_slave_channel(spi->dev, "tx");
 	if (!spi->dma_tx)
@@ -1174,7 +1192,7 @@ static int stm32_spi_probe(struct platform_device *pdev)
 		master->dma_rx = spi->dma_rx;
 
 	if (spi->dma_tx || spi->dma_rx)
-		master->can_dma = stm32_spi_can_dma;
+		master->can_dma = stm32h7_spi_can_dma;
 
 	pm_runtime_set_active(&pdev->dev);
 	pm_runtime_enable(&pdev->dev);
@@ -1228,12 +1246,12 @@ static int stm32_spi_probe(struct platform_device *pdev)
 	return ret;
 }
 
-static int stm32_spi_remove(struct platform_device *pdev)
+static int stm32h7_spi_remove(struct platform_device *pdev)
 {
 	struct spi_master *master = platform_get_drvdata(pdev);
-	struct stm32_spi *spi = spi_master_get_devdata(master);
+	struct stm32h7_spi *spi = spi_master_get_devdata(master);
 
-	stm32_spi_disable(spi);
+	stm32h7_spi_disable(spi);
 
 	if (master->dma_tx)
 		dma_release_channel(master->dma_tx);
@@ -1248,27 +1266,27 @@ static int stm32_spi_remove(struct platform_device *pdev)
 }
 
 #ifdef CONFIG_PM
-static int stm32_spi_runtime_suspend(struct device *dev)
+static int stm32h7_spi_runtime_suspend(struct device *dev)
 {
 	struct spi_master *master = dev_get_drvdata(dev);
-	struct stm32_spi *spi = spi_master_get_devdata(master);
+	struct stm32h7_spi *spi = spi_master_get_devdata(master);
 
 	clk_disable_unprepare(spi->clk);
 
 	return 0;
 }
 
-static int stm32_spi_runtime_resume(struct device *dev)
+static int stm32h7_spi_runtime_resume(struct device *dev)
 {
 	struct spi_master *master = dev_get_drvdata(dev);
-	struct stm32_spi *spi = spi_master_get_devdata(master);
+	struct stm32h7_spi *spi = spi_master_get_devdata(master);
 
 	return clk_prepare_enable(spi->clk);
 }
 #endif
 
 #ifdef CONFIG_PM_SLEEP
-static int stm32_spi_suspend(struct device *dev)
+static int stm32h7_spi_suspend(struct device *dev)
 {
 	struct spi_master *master = dev_get_drvdata(dev);
 	int ret;
@@ -1280,10 +1298,10 @@ static int stm32_spi_suspend(struct device *dev)
 	return pm_runtime_force_suspend(dev);
 }
 
-static int stm32_spi_resume(struct device *dev)
+static int stm32h7_spi_resume(struct device *dev)
 {
 	struct spi_master *master = dev_get_drvdata(dev);
-	struct stm32_spi *spi = spi_master_get_devdata(master);
+	struct stm32h7_spi *spi = spi_master_get_devdata(master);
 	int ret;
 
 	ret = pm_runtime_force_resume(dev);
@@ -1298,23 +1316,23 @@ static int stm32_spi_resume(struct device *dev)
 }
 #endif
 
-static const struct dev_pm_ops stm32_spi_pm_ops = {
-	SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
-	SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend,
-			   stm32_spi_runtime_resume, NULL)
+static const struct dev_pm_ops stm32h7_spi_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(stm32h7_spi_suspend, stm32h7_spi_resume)
+	SET_RUNTIME_PM_OPS(stm32h7_spi_runtime_suspend,
+			   stm32h7_spi_runtime_resume, NULL)
 };
 
-static struct platform_driver stm32_spi_driver = {
-	.probe = stm32_spi_probe,
-	.remove = stm32_spi_remove,
+static struct platform_driver stm32h7_spi_driver = {
+	.probe = stm32h7_spi_probe,
+	.remove = stm32h7_spi_remove,
 	.driver = {
 		.name = DRIVER_NAME,
-		.pm = &stm32_spi_pm_ops,
-		.of_match_table = stm32_spi_of_match,
+		.pm = &stm32h7_spi_pm_ops,
+		.of_match_table = stm32h7_spi_of_match,
 	},
 };
 
-module_platform_driver(stm32_spi_driver);
+module_platform_driver(stm32h7_spi_driver);
 
 MODULE_ALIAS("platform:" DRIVER_NAME);
 MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
-- 
2.7.4

[PATCH 2/5] spi: stm32: rename spi-stm32 to spi-stm32h7

[cezary.gapinski]

From: Cezary Gapinski <cezary.gapinski@gmail.com>

Rename spi-stm32 driver to be related to STM32H7 type.

Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com>
---
 drivers/spi/Kconfig       |    8 +-
 drivers/spi/Makefile      |    2 +-
 drivers/spi/spi-stm32.c   | 1340 ---------------------------------------------
 drivers/spi/spi-stm32h7.c | 1340 +++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 1345 insertions(+), 1345 deletions(-)
 delete mode 100644 drivers/spi/spi-stm32.c
 create mode 100644 drivers/spi/spi-stm32h7.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 7d3a5c9..0151334 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -645,13 +645,13 @@ config SPI_SPRD_ADI
 	help
 	  ADI driver based on SPI for Spreadtrum SoCs.
 
-config SPI_STM32
-	tristate "STMicroelectronics STM32 SPI controller"
+config SPI_STM32H7
+	tristate "STMicroelectronics STM32H7 SPI controller"
 	depends on ARCH_STM32 || COMPILE_TEST
 	help
-	  SPI driver for STMicroelectonics STM32 SoCs.
+	  SPI driver for STMicroelectronics STM32H7 SoCs.
 
-	  STM32 SPI controller supports DMA and PIO modes. When DMA
+	  STM32H7 SPI controller supports DMA and PIO modes. When DMA
 	  is not available, the driver automatically falls back to
 	  PIO mode.
 
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3575205..6f24938 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -94,7 +94,7 @@ obj-$(CONFIG_SPI_SIRF)		+= spi-sirf.o
 obj-$(CONFIG_SPI_SLAVE_MT27XX)          += spi-slave-mt27xx.o
 obj-$(CONFIG_SPI_SPRD)			+= spi-sprd.o
 obj-$(CONFIG_SPI_SPRD_ADI)		+= spi-sprd-adi.o
-obj-$(CONFIG_SPI_STM32) 		+= spi-stm32.o
+obj-$(CONFIG_SPI_STM32H7) 		+= spi-stm32h7.o
 obj-$(CONFIG_SPI_STM32_QSPI) 		+= spi-stm32-qspi.o
 obj-$(CONFIG_SPI_ST_SSC4)		+= spi-st-ssc4.o
 obj-$(CONFIG_SPI_SUN4I)			+= spi-sun4i.o
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
deleted file mode 100644
index eb4d93e..0000000
--- a/drivers/spi/spi-stm32.c
+++ /dev/null
@@ -1,1340 +0,0 @@
-/*
- * STMicroelectronics STM32 SPI Controller driver (master mode only)
- *
- * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
- *
- * License terms: GPL V2.0.
- *
- * spi_stm32 driver is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * spi_stm32 driver is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License along with
- * spi_stm32 driver. If not, see <http://www.gnu.org/licenses/>.
- */
-#include <linux/debugfs.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/dmaengine.h>
-#include <linux/gpio.h>
-#include <linux/interrupt.h>
-#include <linux/iopoll.h>
-#include <linux/module.h>
-#include <linux/of_platform.h>
-#include <linux/pm_runtime.h>
-#include <linux/reset.h>
-#include <linux/spi/spi.h>
-
-#define DRIVER_NAME "spi_stm32"
-
-/* STM32H7 SPI registers */
-#define STM32H7_SPI_CR1			0x00
-#define STM32H7_SPI_CR2			0x04
-#define STM32H7_SPI_CFG1		0x08
-#define STM32H7_SPI_CFG2		0x0C
-#define STM32H7_SPI_IER			0x10
-#define STM32H7_SPI_SR			0x14
-#define STM32H7_SPI_IFCR		0x18
-#define STM32H7_SPI_TXDR		0x20
-#define STM32H7_SPI_RXDR		0x30
-#define STM32H7_SPI_I2SCFGR		0x50
-
-/* STM32H7_SPI_CR1 bit fields */
-#define STM32H7_SPI_CR1_SPE		BIT(0)
-#define STM32H7_SPI_CR1_MASRX		BIT(8)
-#define STM32H7_SPI_CR1_CSTART		BIT(9)
-#define STM32H7_SPI_CR1_CSUSP		BIT(10)
-#define STM32H7_SPI_CR1_HDDIR		BIT(11)
-#define STM32H7_SPI_CR1_SSI		BIT(12)
-
-/* STM32H7_SPI_CR2 bit fields */
-#define STM32H7_SPI_CR2_TSIZE_SHIFT	0
-#define STM32H7_SPI_CR2_TSIZE		GENMASK(15, 0)
-
-/* STM32H7_SPI_CFG1 bit fields */
-#define STM32H7_SPI_CFG1_DSIZE_SHIFT	0
-#define STM32H7_SPI_CFG1_DSIZE		GENMASK(4, 0)
-#define STM32H7_SPI_CFG1_FTHLV_SHIFT	5
-#define STM32H7_SPI_CFG1_FTHLV		GENMASK(8, 5)
-#define STM32H7_SPI_CFG1_RXDMAEN	BIT(14)
-#define STM32H7_SPI_CFG1_TXDMAEN	BIT(15)
-#define STM32H7_SPI_CFG1_MBR_SHIFT	28
-#define STM32H7_SPI_CFG1_MBR		GENMASK(30, 28)
-#define STM32H7_SPI_CFG1_MBR_MIN	0
-#define STM32H7_SPI_CFG1_MBR_MAX	(GENMASK(30, 28) >> 28)
-
-/* STM32H7_SPI_CFG2 bit fields */
-#define STM32H7_SPI_CFG2_MIDI_SHIFT	4
-#define STM32H7_SPI_CFG2_MIDI		GENMASK(7, 4)
-#define STM32H7_SPI_CFG2_COMM_SHIFT	17
-#define STM32H7_SPI_CFG2_COMM		GENMASK(18, 17)
-#define STM32H7_SPI_CFG2_SP_SHIFT	19
-#define STM32H7_SPI_CFG2_SP		GENMASK(21, 19)
-#define STM32H7_SPI_CFG2_MASTER		BIT(22)
-#define STM32H7_SPI_CFG2_LSBFRST	BIT(23)
-#define STM32H7_SPI_CFG2_CPHA		BIT(24)
-#define STM32H7_SPI_CFG2_CPOL		BIT(25)
-#define STM32H7_SPI_CFG2_SSM		BIT(26)
-#define STM32H7_SPI_CFG2_AFCNTR		BIT(31)
-
-/* STM32H7_SPI_IER bit fields */
-#define STM32H7_SPI_IER_RXPIE		BIT(0)
-#define STM32H7_SPI_IER_TXPIE		BIT(1)
-#define STM32H7_SPI_IER_DXPIE		BIT(2)
-#define STM32H7_SPI_IER_EOTIE		BIT(3)
-#define STM32H7_SPI_IER_TXTFIE		BIT(4)
-#define STM32H7_SPI_IER_OVRIE		BIT(6)
-#define STM32H7_SPI_IER_MODFIE		BIT(9)
-#define STM32H7_SPI_IER_ALL		GENMASK(10, 0)
-
-/* STM32H7_SPI_SR bit fields */
-#define STM32H7_SPI_SR_RXP		BIT(0)
-#define STM32H7_SPI_SR_TXP		BIT(1)
-#define STM32H7_SPI_SR_EOT		BIT(3)
-#define STM32H7_SPI_SR_OVR		BIT(6)
-#define STM32H7_SPI_SR_MODF		BIT(9)
-#define STM32H7_SPI_SR_SUSP		BIT(11)
-#define STM32H7_SPI_SR_RXPLVL_SHIFT	13
-#define STM32H7_SPI_SR_RXPLVL		GENMASK(14, 13)
-#define STM32H7_SPI_SR_RXWNE		BIT(15)
-
-/* STM32H7_SPI_IFCR bit fields */
-#define STM32H7_SPI_IFCR_ALL		GENMASK(11, 3)
-
-/* STM32H7_SPI_I2SCFGR bit fields */
-#define STM32H7_SPI_I2SCFGR_I2SMOD	BIT(0)
-
-/* STM32H7 SPI Master Baud Rate min/max divisor */
-#define STM32H7_SPI_MBR_DIV_MIN		(2 << STM32H7_SPI_CFG1_MBR_MIN)
-#define STM32H7_SPI_MBR_DIV_MAX		(2 << STM32H7_SPI_CFG1_MBR_MAX)
-
-/* STM32H7 SPI Communication mode */
-#define STM32H7_SPI_FULL_DUPLEX		0
-#define STM32H7_SPI_SIMPLEX_TX		1
-#define STM32H7_SPI_SIMPLEX_RX		2
-#define STM32H7_SPI_HALF_DUPLEX		3
-
-#define STM32H7_SPI_1HZ_NS		1000000000
-
-/**
- * struct stm32h7_spi - private data of the SPI controller
- * @dev: driver model representation of the controller
- * @master: controller master interface
- * @base: virtual memory area
- * @clk: hw kernel clock feeding the SPI clock generator
- * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
- * @rst: SPI controller reset line
- * @lock: prevent I/O concurrent access
- * @irq: SPI controller interrupt line
- * @fifo_size: size of the embedded fifo in bytes
- * @cur_midi: master inter-data idleness in ns
- * @cur_speed: speed configured in Hz
- * @cur_bpw: number of bits in a single SPI data frame
- * @cur_fthlv: fifo threshold level (data frames in a single data packet)
- * @cur_comm: SPI communication mode
- * @cur_xferlen: current transfer length in bytes
- * @cur_usedma: boolean to know if dma is used in current transfer
- * @tx_buf: data to be written, or NULL
- * @rx_buf: data to be read, or NULL
- * @tx_len: number of data to be written in bytes
- * @rx_len: number of data to be read in bytes
- * @dma_tx: dma channel for TX transfer
- * @dma_rx: dma channel for RX transfer
- * @phys_addr: SPI registers physical base address
- */
-struct stm32h7_spi {
-	struct device *dev;
-	struct spi_master *master;
-	void __iomem *base;
-	struct clk *clk;
-	u32 clk_rate;
-	struct reset_control *rst;
-	spinlock_t lock; /* prevent I/O concurrent access */
-	int irq;
-	unsigned int fifo_size;
-
-	unsigned int cur_midi;
-	unsigned int cur_speed;
-	unsigned int cur_bpw;
-	unsigned int cur_fthlv;
-	unsigned int cur_comm;
-	unsigned int cur_xferlen;
-	bool cur_usedma;
-
-	const void *tx_buf;
-	void *rx_buf;
-	int tx_len;
-	int rx_len;
-	struct dma_chan *dma_tx;
-	struct dma_chan *dma_rx;
-	dma_addr_t phys_addr;
-};
-
-static inline void stm32h7_spi_set_bits(struct stm32h7_spi *spi,
-					u32 offset, u32 bits)
-{
-	writel_relaxed(readl_relaxed(spi->base + offset) | bits,
-		       spi->base + offset);
-}
-
-static inline void stm32h7_spi_clr_bits(struct stm32h7_spi *spi,
-					u32 offset, u32 bits)
-{
-	writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
-		       spi->base + offset);
-}
-
-/**
- * stm32h7_spi_get_fifo_size - Return fifo size
- * @spi: pointer to the spi controller data structure
- */
-static int stm32h7_spi_get_fifo_size(struct stm32h7_spi *spi)
-{
-	unsigned long flags;
-	u32 count = 0;
-
-	spin_lock_irqsave(&spi->lock, flags);
-
-	stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
-
-	while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
-		writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
-
-	stm32h7_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
-
-	spin_unlock_irqrestore(&spi->lock, flags);
-
-	dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
-
-	return count;
-}
-
-/**
- * stm32h7_spi_get_bpw_mask - Return bits per word mask
- * @spi: pointer to the spi controller data structure
- */
-static int stm32h7_spi_get_bpw_mask(struct stm32h7_spi *spi)
-{
-	unsigned long flags;
-	u32 cfg1, max_bpw;
-
-	spin_lock_irqsave(&spi->lock, flags);
-
-	/*
-	 * The most significant bit at DSIZE bit field is reserved when the
-	 * maximum data size of periperal instances is limited to 16-bit
-	 */
-	stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
-
-	cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
-	max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >>
-		  STM32H7_SPI_CFG1_DSIZE_SHIFT;
-	max_bpw += 1;
-
-	spin_unlock_irqrestore(&spi->lock, flags);
-
-	dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
-
-	return SPI_BPW_RANGE_MASK(4, max_bpw);
-}
-
-/**
- * stm32h7_spi_prepare_mbr - Determine STM32H7_SPI_CFG1.MBR value
- * @spi: pointer to the spi controller data structure
- * @speed_hz: requested speed
- *
- * Return STM32H7_SPI_CFG1.MBR value in case of success or -EINVAL
- */
-static int stm32h7_spi_prepare_mbr(struct stm32h7_spi *spi, u32 speed_hz)
-{
-	u32 div, mbrdiv;
-
-	div = DIV_ROUND_UP(spi->clk_rate, speed_hz);
-
-	/*
-	 * SPI framework set xfer->speed_hz to master->max_speed_hz if
-	 * xfer->speed_hz is greater than master->max_speed_hz, and it returns
-	 * an error when xfer->speed_hz is lower than master->min_speed_hz, so
-	 * no need to check it there.
-	 * However, we need to ensure the following calculations.
-	 */
-	if (div < STM32H7_SPI_MBR_DIV_MIN ||
-	    div > STM32H7_SPI_MBR_DIV_MAX)
-		return -EINVAL;
-
-	/* Determine the first power of 2 greater than or equal to div */
-	if (div & (div - 1))
-		mbrdiv = fls(div);
-	else
-		mbrdiv = fls(div) - 1;
-
-	spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
-
-	return mbrdiv - 1;
-}
-
-/**
- * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
- * @spi: pointer to the spi controller data structure
- */
-static u32 stm32h7_spi_prepare_fthlv(struct stm32h7_spi *spi)
-{
-	u32 fthlv, half_fifo;
-
-	/* data packet should not exceed 1/2 of fifo space */
-	half_fifo = (spi->fifo_size / 2);
-
-	if (spi->cur_bpw <= 8)
-		fthlv = half_fifo;
-	else if (spi->cur_bpw <= 16)
-		fthlv = half_fifo / 2;
-	else
-		fthlv = half_fifo / 4;
-
-	/* align packet size with data registers access */
-	if (spi->cur_bpw > 8)
-		fthlv -= (fthlv % 2); /* multiple of 2 */
-	else
-		fthlv -= (fthlv % 4); /* multiple of 4 */
-
-	return fthlv;
-}
-
-/**
- * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
- * @spi: pointer to the spi controller data structure
- *
- * Read from tx_buf depends on remaining bytes to avoid to read beyond
- * tx_buf end.
- */
-static void stm32h7_spi_write_txfifo(struct stm32h7_spi *spi)
-{
-	while ((spi->tx_len > 0) &&
-	       (readl_relaxed(spi->base + STM32H7_SPI_SR) &
-		STM32H7_SPI_SR_TXP)) {
-		u32 offs = spi->cur_xferlen - spi->tx_len;
-
-		if (spi->tx_len >= sizeof(u32)) {
-			const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
-
-			writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
-			spi->tx_len -= sizeof(u32);
-		} else if (spi->tx_len >= sizeof(u16)) {
-			const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
-
-			writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
-			spi->tx_len -= sizeof(u16);
-		} else {
-			const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
-
-			writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
-			spi->tx_len -= sizeof(u8);
-		}
-	}
-
-	dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
-}
-
-/**
- * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
- * @spi: pointer to the spi controller data structure
- *
- * Write in rx_buf depends on remaining bytes to avoid to write beyond
- * rx_buf end.
- */
-static void stm32h7_spi_read_rxfifo(struct stm32h7_spi *spi, bool flush)
-{
-	u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
-	u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
-		     STM32H7_SPI_SR_RXPLVL_SHIFT;
-
-	while ((spi->rx_len > 0) &&
-	       ((sr & STM32H7_SPI_SR_RXP) ||
-		(flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
-		u32 offs = spi->cur_xferlen - spi->rx_len;
-
-		if ((spi->rx_len >= sizeof(u32)) ||
-		    (flush && (sr & STM32H7_SPI_SR_RXWNE))) {
-			u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
-
-			*rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
-			spi->rx_len -= sizeof(u32);
-		} else if ((spi->rx_len >= sizeof(u16)) ||
-			   (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) {
-			u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
-
-			*rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
-			spi->rx_len -= sizeof(u16);
-		} else {
-			u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
-
-			*rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
-			spi->rx_len -= sizeof(u8);
-		}
-
-		sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
-		rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
-			 STM32H7_SPI_SR_RXPLVL_SHIFT;
-	}
-
-	dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
-		flush ? "(flush)" : "", spi->rx_len);
-}
-
-/**
- * stm32h7_spi_enable - Enable SPI controller
- * @spi: pointer to the spi controller data structure
- *
- * SPI data transfer is enabled but spi_ker_ck is idle.
- * STM32H7_SPI_CFG1 and STM32H7_SPI_CFG2 are now write protected.
- */
-static void stm32h7_spi_enable(struct stm32h7_spi *spi)
-{
-	dev_dbg(spi->dev, "enable controller\n");
-
-	stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
-}
-
-/**
- * stm32h7_spi_disable - Disable SPI controller
- * @spi: pointer to the spi controller data structure
- *
- * RX-Fifo is flushed when SPI controller is disabled. To prevent any data
- * loss, use stm32h7_spi_read_rxfifo(flush) to read the remaining bytes in
- * RX-Fifo.
- */
-static void stm32h7_spi_disable(struct stm32h7_spi *spi)
-{
-	unsigned long flags;
-	u32 cr1, sr;
-
-	dev_dbg(spi->dev, "disable controller\n");
-
-	spin_lock_irqsave(&spi->lock, flags);
-
-	cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
-
-	if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
-		spin_unlock_irqrestore(&spi->lock, flags);
-		return;
-	}
-
-	/* Wait on EOT or suspend the flow */
-	if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR,
-					      sr, !(sr & STM32H7_SPI_SR_EOT),
-					      10, 100000) < 0) {
-		if (cr1 & STM32H7_SPI_CR1_CSTART) {
-			writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP,
-				       spi->base + STM32H7_SPI_CR1);
-			if (readl_relaxed_poll_timeout_atomic(
-						spi->base + STM32H7_SPI_SR,
-						sr, !(sr & STM32H7_SPI_SR_SUSP),
-						10, 100000) < 0)
-				dev_warn(spi->dev,
-					 "Suspend request timeout\n");
-		}
-	}
-
-	if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0))
-		stm32h7_spi_read_rxfifo(spi, true);
-
-	if (spi->cur_usedma && spi->tx_buf)
-		dmaengine_terminate_all(spi->dma_tx);
-	if (spi->cur_usedma && spi->rx_buf)
-		dmaengine_terminate_all(spi->dma_rx);
-
-	stm32h7_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
-
-	stm32h7_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
-						    STM32H7_SPI_CFG1_RXDMAEN);
-
-	/* Disable interrupts and clear status flags */
-	writel_relaxed(0, spi->base + STM32H7_SPI_IER);
-	writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
-
-	spin_unlock_irqrestore(&spi->lock, flags);
-}
-
-/**
- * stm32h7_spi_can_dma - Determine if the transfer is eligible for DMA use
- *
- * If the current transfer size is greater than fifo size, use DMA.
- */
-static bool stm32h7_spi_can_dma(struct spi_master *master,
-				struct spi_device *spi_dev,
-				struct spi_transfer *transfer)
-{
-	struct stm32h7_spi *spi = spi_master_get_devdata(master);
-
-	dev_dbg(spi->dev, "%s: %s\n", __func__,
-		(transfer->len > spi->fifo_size) ? "true" : "false");
-
-	return (transfer->len > spi->fifo_size);
-}
-
-/**
- * stm32h7_spi_irq - Interrupt handler for SPI controller events
- * @irq: interrupt line
- * @dev_id: SPI controller master interface
- */
-static irqreturn_t stm32h7_spi_irq(int irq, void *dev_id)
-{
-	struct spi_master *master = dev_id;
-	struct stm32h7_spi *spi = spi_master_get_devdata(master);
-	u32 sr, ier, mask;
-	unsigned long flags;
-	bool end = false;
-
-	spin_lock_irqsave(&spi->lock, flags);
-
-	sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
-	ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
-
-	mask = ier;
-	/* EOTIE is triggered on EOT, SUSP and TXC events. */
-	mask |= STM32H7_SPI_SR_SUSP;
-	/*
-	 * When TXTF is set, DXPIE and TXPIE are cleared. So in case of
-	 * Full-Duplex, need to poll RXP event to know if there are remaining
-	 * data, before disabling SPI.
-	 */
-	if (spi->rx_buf && !spi->cur_usedma)
-		mask |= STM32H7_SPI_SR_RXP;
-
-	if (!(sr & mask)) {
-		dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
-			sr, ier);
-		spin_unlock_irqrestore(&spi->lock, flags);
-		return IRQ_NONE;
-	}
-
-	if (sr & STM32H7_SPI_SR_SUSP) {
-		dev_warn(spi->dev, "Communication suspended\n");
-		if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
-			stm32h7_spi_read_rxfifo(spi, false);
-		/*
-		 * If communication is suspended while using DMA, it means
-		 * that something went wrong, so stop the current transfer
-		 */
-		if (spi->cur_usedma)
-			end = true;
-	}
-
-	if (sr & STM32H7_SPI_SR_MODF) {
-		dev_warn(spi->dev, "Mode fault: transfer aborted\n");
-		end = true;
-	}
-
-	if (sr & STM32H7_SPI_SR_OVR) {
-		dev_warn(spi->dev, "Overrun: received value discarded\n");
-		if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
-			stm32h7_spi_read_rxfifo(spi, false);
-		/*
-		 * If overrun is detected while using DMA, it means that
-		 * something went wrong, so stop the current transfer
-		 */
-		if (spi->cur_usedma)
-			end = true;
-	}
-
-	if (sr & STM32H7_SPI_SR_EOT) {
-		if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
-			stm32h7_spi_read_rxfifo(spi, true);
-		end = true;
-	}
-
-	if (sr & STM32H7_SPI_SR_TXP)
-		if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
-			stm32h7_spi_write_txfifo(spi);
-
-	if (sr & STM32H7_SPI_SR_RXP)
-		if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
-			stm32h7_spi_read_rxfifo(spi, false);
-
-	writel_relaxed(mask, spi->base + STM32H7_SPI_IFCR);
-
-	spin_unlock_irqrestore(&spi->lock, flags);
-
-	if (end) {
-		spi_finalize_current_transfer(master);
-		stm32h7_spi_disable(spi);
-	}
-
-	return IRQ_HANDLED;
-}
-
-/**
- * stm32h7_spi_setup - setup device chip select
- */
-static int stm32h7_spi_setup(struct spi_device *spi_dev)
-{
-	int ret = 0;
-
-	if (!gpio_is_valid(spi_dev->cs_gpio)) {
-		dev_err(&spi_dev->dev, "%d is not a valid gpio\n",
-			spi_dev->cs_gpio);
-		return -EINVAL;
-	}
-
-	dev_dbg(&spi_dev->dev, "%s: set gpio%d output %s\n", __func__,
-		spi_dev->cs_gpio,
-		(spi_dev->mode & SPI_CS_HIGH) ? "low" : "high");
-
-	ret = gpio_direction_output(spi_dev->cs_gpio,
-				    !(spi_dev->mode & SPI_CS_HIGH));
-
-	return ret;
-}
-
-/**
- * stm32h7_spi_prepare_msg - set up the controller to transfer a single message
- */
-static int stm32h7_spi_prepare_msg(struct spi_master *master,
-				   struct spi_message *msg)
-{
-	struct stm32h7_spi *spi = spi_master_get_devdata(master);
-	struct spi_device *spi_dev = msg->spi;
-	struct device_node *np = spi_dev->dev.of_node;
-	unsigned long flags;
-	u32 cfg2_clrb = 0, cfg2_setb = 0;
-
-	/* SPI slave device may need time between data frames */
-	spi->cur_midi = 0;
-	if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
-		dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
-
-	if (spi_dev->mode & SPI_CPOL)
-		cfg2_setb |= STM32H7_SPI_CFG2_CPOL;
-	else
-		cfg2_clrb |= STM32H7_SPI_CFG2_CPOL;
-
-	if (spi_dev->mode & SPI_CPHA)
-		cfg2_setb |= STM32H7_SPI_CFG2_CPHA;
-	else
-		cfg2_clrb |= STM32H7_SPI_CFG2_CPHA;
-
-	if (spi_dev->mode & SPI_LSB_FIRST)
-		cfg2_setb |= STM32H7_SPI_CFG2_LSBFRST;
-	else
-		cfg2_clrb |= STM32H7_SPI_CFG2_LSBFRST;
-
-	dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
-		spi_dev->mode & SPI_CPOL,
-		spi_dev->mode & SPI_CPHA,
-		spi_dev->mode & SPI_LSB_FIRST,
-		spi_dev->mode & SPI_CS_HIGH);
-
-	spin_lock_irqsave(&spi->lock, flags);
-
-	if (cfg2_clrb || cfg2_setb)
-		writel_relaxed(
-			(readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
-				~cfg2_clrb) | cfg2_setb,
-			       spi->base + STM32H7_SPI_CFG2);
-
-	spin_unlock_irqrestore(&spi->lock, flags);
-
-	return 0;
-}
-
-/**
- * stm32h7_spi_dma_cb - dma callback
- *
- * DMA callback is called when the transfer is complete or when an error
- * occurs. If the transfer is complete, EOT flag is raised.
- */
-static void stm32h7_spi_dma_cb(void *data)
-{
-	struct stm32h7_spi *spi = data;
-	unsigned long flags;
-	u32 sr;
-
-	spin_lock_irqsave(&spi->lock, flags);
-
-	sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
-
-	spin_unlock_irqrestore(&spi->lock, flags);
-
-	if (!(sr & STM32H7_SPI_SR_EOT))
-		dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr);
-
-	/* Now wait for EOT, or SUSP or OVR in case of error */
-}
-
-/**
- * stm32h7_spi_dma_config - configure dma slave channel depending on current
- *			    transfer bits_per_word.
- */
-static void stm32h7_spi_dma_config(struct stm32h7_spi *spi,
-				   struct dma_slave_config *dma_conf,
-				   enum dma_transfer_direction dir)
-{
-	enum dma_slave_buswidth buswidth;
-	u32 maxburst;
-
-	if (spi->cur_bpw <= 8)
-		buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
-	else if (spi->cur_bpw <= 16)
-		buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
-	else
-		buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
-
-	/* Valid for DMA Half or Full Fifo threshold */
-	if (spi->cur_fthlv == 2)
-		maxburst = 1;
-	else
-		maxburst = spi->cur_fthlv;
-
-	memset(dma_conf, 0, sizeof(struct dma_slave_config));
-	dma_conf->direction = dir;
-	if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
-		dma_conf->src_addr = spi->phys_addr + STM32H7_SPI_RXDR;
-		dma_conf->src_addr_width = buswidth;
-		dma_conf->src_maxburst = maxburst;
-
-		dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
-			buswidth, maxburst);
-	} else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
-		dma_conf->dst_addr = spi->phys_addr + STM32H7_SPI_TXDR;
-		dma_conf->dst_addr_width = buswidth;
-		dma_conf->dst_maxburst = maxburst;
-
-		dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
-			buswidth, maxburst);
-	}
-}
-
-/**
- * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
- *				  interrupts
- *
- * It must returns 0 if the transfer is finished or 1 if the transfer is still
- * in progress.
- */
-static int stm32h7_spi_transfer_one_irq(struct stm32h7_spi *spi)
-{
-	unsigned long flags;
-	u32 ier = 0;
-
-	/* Enable the interrupts relative to the current communication mode */
-	if (spi->tx_buf && spi->rx_buf)	/* Full Duplex */
-		ier |= STM32H7_SPI_IER_DXPIE;
-	else if (spi->tx_buf)		/* Half-Duplex TX dir or Simplex TX */
-		ier |= STM32H7_SPI_IER_TXPIE;
-	else if (spi->rx_buf)		/* Half-Duplex RX dir or Simplex RX */
-		ier |= STM32H7_SPI_IER_RXPIE;
-
-	/* Enable the interrupts relative to the end of transfer */
-	ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
-	       STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
-
-	spin_lock_irqsave(&spi->lock, flags);
-
-	stm32h7_spi_enable(spi);
-
-	/* Be sure to have data in fifo before starting data transfer */
-	if (spi->tx_buf)
-		stm32h7_spi_write_txfifo(spi);
-
-	stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
-
-	writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
-
-	spin_unlock_irqrestore(&spi->lock, flags);
-
-	return 1;
-}
-
-/**
- * stm32h7_spi_transfer_one_dma - transfer a single spi_transfer using DMA
- *
- * It must returns 0 if the transfer is finished or 1 if the transfer is still
- * in progress.
- */
-static int stm32h7_spi_transfer_one_dma(struct stm32h7_spi *spi,
-					struct spi_transfer *xfer)
-{
-	struct dma_slave_config tx_dma_conf, rx_dma_conf;
-	struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
-	unsigned long flags;
-	u32 ier = 0;
-
-	spin_lock_irqsave(&spi->lock, flags);
-
-	rx_dma_desc = NULL;
-	if (spi->rx_buf) {
-		stm32h7_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
-		dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
-
-		/* Enable Rx DMA request */
-		stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG1,
-				   STM32H7_SPI_CFG1_RXDMAEN);
-
-		rx_dma_desc = dmaengine_prep_slave_sg(
-					spi->dma_rx, xfer->rx_sg.sgl,
-					xfer->rx_sg.nents,
-					rx_dma_conf.direction,
-					DMA_PREP_INTERRUPT);
-	}
-
-	tx_dma_desc = NULL;
-	if (spi->tx_buf) {
-		stm32h7_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
-		dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
-
-		tx_dma_desc = dmaengine_prep_slave_sg(
-					spi->dma_tx, xfer->tx_sg.sgl,
-					xfer->tx_sg.nents,
-					tx_dma_conf.direction,
-					DMA_PREP_INTERRUPT);
-	}
-
-	if ((spi->tx_buf && !tx_dma_desc) ||
-	    (spi->rx_buf && !rx_dma_desc))
-		goto dma_desc_error;
-
-	if (rx_dma_desc) {
-		rx_dma_desc->callback = stm32h7_spi_dma_cb;
-		rx_dma_desc->callback_param = spi;
-
-		if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
-			dev_err(spi->dev, "Rx DMA submit failed\n");
-			goto dma_desc_error;
-		}
-		/* Enable Rx DMA channel */
-		dma_async_issue_pending(spi->dma_rx);
-	}
-
-	if (tx_dma_desc) {
-		if (spi->cur_comm == STM32H7_SPI_SIMPLEX_TX) {
-			tx_dma_desc->callback = stm32h7_spi_dma_cb;
-			tx_dma_desc->callback_param = spi;
-		}
-
-		if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
-			dev_err(spi->dev, "Tx DMA submit failed\n");
-			goto dma_submit_error;
-		}
-		/* Enable Tx DMA channel */
-		dma_async_issue_pending(spi->dma_tx);
-
-		/* Enable Tx DMA request */
-		stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG1,
-				     STM32H7_SPI_CFG1_TXDMAEN);
-	}
-
-	/* Enable the interrupts relative to the end of transfer */
-	ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
-	       STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
-	writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
-
-	stm32h7_spi_enable(spi);
-
-	stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
-
-	spin_unlock_irqrestore(&spi->lock, flags);
-
-	return 1;
-
-dma_submit_error:
-	if (spi->rx_buf)
-		dmaengine_terminate_all(spi->dma_rx);
-
-dma_desc_error:
-	stm32h7_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN);
-
-	spin_unlock_irqrestore(&spi->lock, flags);
-
-	dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
-
-	return stm32h7_spi_transfer_one_irq(spi);
-}
-
-/**
- * stm32h7_spi_transfer_one_setup - common setup to transfer a single
- *				    spi_transfer either using DMA or
- *				    interrupts.
- */
-static int stm32h7_spi_transfer_one_setup(struct stm32h7_spi *spi,
-					  struct spi_device *spi_dev,
-					  struct spi_transfer *transfer)
-{
-	unsigned long flags;
-	u32 cfg1_clrb = 0, cfg1_setb = 0, cfg2_clrb = 0, cfg2_setb = 0;
-	u32 mode, nb_words;
-	int ret = 0;
-
-	spin_lock_irqsave(&spi->lock, flags);
-
-	if (spi->cur_bpw != transfer->bits_per_word) {
-		u32 bpw, fthlv;
-
-		spi->cur_bpw = transfer->bits_per_word;
-		bpw = spi->cur_bpw - 1;
-
-		cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
-		cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
-			     STM32H7_SPI_CFG1_DSIZE;
-
-		spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi);
-		fthlv = spi->cur_fthlv - 1;
-
-		cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
-		cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
-			     STM32H7_SPI_CFG1_FTHLV;
-	}
-
-	if (spi->cur_speed != transfer->speed_hz) {
-		int mbr;
-
-		/* Update spi->cur_speed with real clock speed */
-		mbr = stm32h7_spi_prepare_mbr(spi, transfer->speed_hz);
-		if (mbr < 0) {
-			ret = mbr;
-			goto out;
-		}
-
-		transfer->speed_hz = spi->cur_speed;
-
-		cfg1_clrb |= STM32H7_SPI_CFG1_MBR;
-		cfg1_setb |= ((u32)mbr << STM32H7_SPI_CFG1_MBR_SHIFT) &
-			     STM32H7_SPI_CFG1_MBR;
-	}
-
-	if (cfg1_clrb || cfg1_setb)
-		writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
-				~cfg1_clrb) | cfg1_setb,
-			       spi->base + STM32H7_SPI_CFG1);
-
-	mode = STM32H7_SPI_FULL_DUPLEX;
-	if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
-		/*
-		 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
-		 * is forbidden und unvalidated by SPI subsystem so depending
-		 * on the valid buffer, we can determine the direction of the
-		 * transfer.
-		 */
-		mode = STM32H7_SPI_HALF_DUPLEX;
-		if (!transfer->tx_buf)
-			stm32h7_spi_clr_bits(spi, STM32H7_SPI_CR1,
-					     STM32H7_SPI_CR1_HDDIR);
-		else if (!transfer->rx_buf)
-			stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1,
-					     STM32H7_SPI_CR1_HDDIR);
-	} else {
-		if (!transfer->tx_buf)
-			mode = STM32H7_SPI_SIMPLEX_RX;
-		else if (!transfer->rx_buf)
-			mode = STM32H7_SPI_SIMPLEX_TX;
-	}
-	if (spi->cur_comm != mode) {
-		spi->cur_comm = mode;
-
-		cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
-		cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) &
-			     STM32H7_SPI_CFG2_COMM;
-	}
-
-	cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
-	if ((transfer->len > 1) && (spi->cur_midi > 0)) {
-		u32 sck_period_ns = DIV_ROUND_UP(STM32H7_SPI_1HZ_NS,
-						 spi->cur_speed);
-		u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
-			       (u32)STM32H7_SPI_CFG2_MIDI >>
-			       STM32H7_SPI_CFG2_MIDI_SHIFT);
-
-		dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
-			sck_period_ns, midi, midi * sck_period_ns);
-
-		cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) &
-			     STM32H7_SPI_CFG2_MIDI;
-	}
-
-	if (cfg2_clrb || cfg2_setb)
-		writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
-				~cfg2_clrb) | cfg2_setb,
-			       spi->base + STM32H7_SPI_CFG2);
-
-	if (spi->cur_bpw <= 8)
-		nb_words = transfer->len;
-	else if (spi->cur_bpw <= 16)
-		nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
-	else
-		nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
-	nb_words <<= STM32H7_SPI_CR2_TSIZE_SHIFT;
-
-	if (nb_words <= STM32H7_SPI_CR2_TSIZE) {
-		writel_relaxed(nb_words, spi->base + STM32H7_SPI_CR2);
-	} else {
-		ret = -EMSGSIZE;
-		goto out;
-	}
-
-	spi->cur_xferlen = transfer->len;
-
-	dev_dbg(spi->dev, "transfer communication mode set to %d\n",
-		spi->cur_comm);
-	dev_dbg(spi->dev,
-		"data frame of %d-bit, data packet of %d data frames\n",
-		spi->cur_bpw, spi->cur_fthlv);
-	dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
-	dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
-		spi->cur_xferlen, nb_words);
-	dev_dbg(spi->dev, "dma %s\n",
-		(spi->cur_usedma) ? "enabled" : "disabled");
-
-out:
-	spin_unlock_irqrestore(&spi->lock, flags);
-
-	return ret;
-}
-
-/**
- * stm32h7_spi_transfer_one - transfer a single spi_transfer
- *
- * It must return 0 if the transfer is finished or 1 if the transfer is still
- * in progress.
- */
-static int stm32h7_spi_transfer_one(struct spi_master *master,
-				    struct spi_device *spi_dev,
-				    struct spi_transfer *transfer)
-{
-	struct stm32h7_spi *spi = spi_master_get_devdata(master);
-	int ret;
-
-	spi->tx_buf = transfer->tx_buf;
-	spi->rx_buf = transfer->rx_buf;
-	spi->tx_len = spi->tx_buf ? transfer->len : 0;
-	spi->rx_len = spi->rx_buf ? transfer->len : 0;
-
-	spi->cur_usedma = (master->can_dma &&
-			   stm32h7_spi_can_dma(master, spi_dev, transfer));
-
-	ret = stm32h7_spi_transfer_one_setup(spi, spi_dev, transfer);
-	if (ret) {
-		dev_err(spi->dev, "SPI transfer setup failed\n");
-		return ret;
-	}
-
-	if (spi->cur_usedma)
-		return stm32h7_spi_transfer_one_dma(spi, transfer);
-	else
-		return stm32h7_spi_transfer_one_irq(spi);
-}
-
-/**
- * stm32h7_spi_unprepare_msg - relax the hardware
- *
- * Normally, if TSIZE has been configured, we should relax the hardware at the
- * reception of the EOT interrupt. But in case of error, EOT will not be
- * raised. So the subsystem unprepare_message call allows us to properly
- * complete the transfer from an hardware point of view.
- */
-static int stm32h7_spi_unprepare_msg(struct spi_master *master,
-				     struct spi_message *msg)
-{
-	struct stm32h7_spi *spi = spi_master_get_devdata(master);
-
-	stm32h7_spi_disable(spi);
-
-	return 0;
-}
-
-/**
- * stm32h7_spi_config - Configure SPI controller as SPI master
- */
-static int stm32h7_spi_config(struct stm32h7_spi *spi)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&spi->lock, flags);
-
-	/* Ensure I2SMOD bit is kept cleared */
-	stm32h7_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
-			     STM32H7_SPI_I2SCFGR_I2SMOD);
-
-	/*
-	 * - SS input value high
-	 * - transmitter half duplex direction
-	 * - automatic communication suspend when RX-Fifo is full
-	 */
-	stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI |
-						   STM32H7_SPI_CR1_HDDIR |
-						   STM32H7_SPI_CR1_MASRX);
-
-	/*
-	 * - Set the master mode (default Motorola mode)
-	 * - Consider 1 master/n slaves configuration and
-	 *   SS input value is determined by the SSI bit
-	 * - keep control of all associated GPIOs
-	 */
-	stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER |
-						    STM32H7_SPI_CFG2_SSM |
-						    STM32H7_SPI_CFG2_AFCNTR);
-
-	spin_unlock_irqrestore(&spi->lock, flags);
-
-	return 0;
-}
-
-static const struct of_device_id stm32h7_spi_of_match[] = {
-	{ .compatible = "st,stm32h7-spi", },
-	{},
-};
-MODULE_DEVICE_TABLE(of, stm32h7_spi_of_match);
-
-static int stm32h7_spi_probe(struct platform_device *pdev)
-{
-	struct spi_master *master;
-	struct stm32h7_spi *spi;
-	struct resource *res;
-	int i, ret;
-
-	master = spi_alloc_master(&pdev->dev, sizeof(struct stm32h7_spi));
-	if (!master) {
-		dev_err(&pdev->dev, "spi master allocation failed\n");
-		return -ENOMEM;
-	}
-	platform_set_drvdata(pdev, master);
-
-	spi = spi_master_get_devdata(master);
-	spi->dev = &pdev->dev;
-	spi->master = master;
-	spin_lock_init(&spi->lock);
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	spi->base = devm_ioremap_resource(&pdev->dev, res);
-	if (IS_ERR(spi->base)) {
-		ret = PTR_ERR(spi->base);
-		goto err_master_put;
-	}
-	spi->phys_addr = (dma_addr_t)res->start;
-
-	spi->irq = platform_get_irq(pdev, 0);
-	if (spi->irq <= 0) {
-		dev_err(&pdev->dev, "no irq: %d\n", spi->irq);
-		ret = -ENOENT;
-		goto err_master_put;
-	}
-	ret = devm_request_threaded_irq(&pdev->dev, spi->irq, NULL,
-					stm32h7_spi_irq, IRQF_ONESHOT,
-					pdev->name, master);
-	if (ret) {
-		dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
-			ret);
-		goto err_master_put;
-	}
-
-	spi->clk = devm_clk_get(&pdev->dev, 0);
-	if (IS_ERR(spi->clk)) {
-		ret = PTR_ERR(spi->clk);
-		dev_err(&pdev->dev, "clk get failed: %d\n", ret);
-		goto err_master_put;
-	}
-
-	ret = clk_prepare_enable(spi->clk);
-	if (ret) {
-		dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
-		goto err_master_put;
-	}
-	spi->clk_rate = clk_get_rate(spi->clk);
-	if (!spi->clk_rate) {
-		dev_err(&pdev->dev, "clk rate = 0\n");
-		ret = -EINVAL;
-		goto err_clk_disable;
-	}
-
-	spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
-	if (!IS_ERR(spi->rst)) {
-		reset_control_assert(spi->rst);
-		udelay(2);
-		reset_control_deassert(spi->rst);
-	}
-
-	spi->fifo_size = stm32h7_spi_get_fifo_size(spi);
-
-	ret = stm32h7_spi_config(spi);
-	if (ret) {
-		dev_err(&pdev->dev, "controller configuration failed: %d\n",
-			ret);
-		goto err_clk_disable;
-	}
-
-	master->dev.of_node = pdev->dev.of_node;
-	master->auto_runtime_pm = true;
-	master->bus_num = pdev->id;
-	master->mode_bits = SPI_MODE_3 | SPI_CS_HIGH | SPI_LSB_FIRST |
-			    SPI_3WIRE | SPI_LOOP;
-	master->bits_per_word_mask = stm32h7_spi_get_bpw_mask(spi);
-	master->max_speed_hz = spi->clk_rate / STM32H7_SPI_MBR_DIV_MIN;
-	master->min_speed_hz = spi->clk_rate / STM32H7_SPI_MBR_DIV_MAX;
-	master->setup = stm32h7_spi_setup;
-	master->prepare_message = stm32h7_spi_prepare_msg;
-	master->transfer_one = stm32h7_spi_transfer_one;
-	master->unprepare_message = stm32h7_spi_unprepare_msg;
-
-	spi->dma_tx = dma_request_slave_channel(spi->dev, "tx");
-	if (!spi->dma_tx)
-		dev_warn(&pdev->dev, "failed to request tx dma channel\n");
-	else
-		master->dma_tx = spi->dma_tx;
-
-	spi->dma_rx = dma_request_slave_channel(spi->dev, "rx");
-	if (!spi->dma_rx)
-		dev_warn(&pdev->dev, "failed to request rx dma channel\n");
-	else
-		master->dma_rx = spi->dma_rx;
-
-	if (spi->dma_tx || spi->dma_rx)
-		master->can_dma = stm32h7_spi_can_dma;
-
-	pm_runtime_set_active(&pdev->dev);
-	pm_runtime_enable(&pdev->dev);
-
-	ret = devm_spi_register_master(&pdev->dev, master);
-	if (ret) {
-		dev_err(&pdev->dev, "spi master registration failed: %d\n",
-			ret);
-		goto err_dma_release;
-	}
-
-	if (!master->cs_gpios) {
-		dev_err(&pdev->dev, "no CS gpios available\n");
-		ret = -EINVAL;
-		goto err_dma_release;
-	}
-
-	for (i = 0; i < master->num_chipselect; i++) {
-		if (!gpio_is_valid(master->cs_gpios[i])) {
-			dev_err(&pdev->dev, "%i is not a valid gpio\n",
-				master->cs_gpios[i]);
-			ret = -EINVAL;
-			goto err_dma_release;
-		}
-
-		ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
-					DRIVER_NAME);
-		if (ret) {
-			dev_err(&pdev->dev, "can't get CS gpio %i\n",
-				master->cs_gpios[i]);
-			goto err_dma_release;
-		}
-	}
-
-	dev_info(&pdev->dev, "driver initialized\n");
-
-	return 0;
-
-err_dma_release:
-	if (spi->dma_tx)
-		dma_release_channel(spi->dma_tx);
-	if (spi->dma_rx)
-		dma_release_channel(spi->dma_rx);
-
-	pm_runtime_disable(&pdev->dev);
-err_clk_disable:
-	clk_disable_unprepare(spi->clk);
-err_master_put:
-	spi_master_put(master);
-
-	return ret;
-}
-
-static int stm32h7_spi_remove(struct platform_device *pdev)
-{
-	struct spi_master *master = platform_get_drvdata(pdev);
-	struct stm32h7_spi *spi = spi_master_get_devdata(master);
-
-	stm32h7_spi_disable(spi);
-
-	if (master->dma_tx)
-		dma_release_channel(master->dma_tx);
-	if (master->dma_rx)
-		dma_release_channel(master->dma_rx);
-
-	clk_disable_unprepare(spi->clk);
-
-	pm_runtime_disable(&pdev->dev);
-
-	return 0;
-}
-
-#ifdef CONFIG_PM
-static int stm32h7_spi_runtime_suspend(struct device *dev)
-{
-	struct spi_master *master = dev_get_drvdata(dev);
-	struct stm32h7_spi *spi = spi_master_get_devdata(master);
-
-	clk_disable_unprepare(spi->clk);
-
-	return 0;
-}
-
-static int stm32h7_spi_runtime_resume(struct device *dev)
-{
-	struct spi_master *master = dev_get_drvdata(dev);
-	struct stm32h7_spi *spi = spi_master_get_devdata(master);
-
-	return clk_prepare_enable(spi->clk);
-}
-#endif
-
-#ifdef CONFIG_PM_SLEEP
-static int stm32h7_spi_suspend(struct device *dev)
-{
-	struct spi_master *master = dev_get_drvdata(dev);
-	int ret;
-
-	ret = spi_master_suspend(master);
-	if (ret)
-		return ret;
-
-	return pm_runtime_force_suspend(dev);
-}
-
-static int stm32h7_spi_resume(struct device *dev)
-{
-	struct spi_master *master = dev_get_drvdata(dev);
-	struct stm32h7_spi *spi = spi_master_get_devdata(master);
-	int ret;
-
-	ret = pm_runtime_force_resume(dev);
-	if (ret)
-		return ret;
-
-	ret = spi_master_resume(master);
-	if (ret)
-		clk_disable_unprepare(spi->clk);
-
-	return ret;
-}
-#endif
-
-static const struct dev_pm_ops stm32h7_spi_pm_ops = {
-	SET_SYSTEM_SLEEP_PM_OPS(stm32h7_spi_suspend, stm32h7_spi_resume)
-	SET_RUNTIME_PM_OPS(stm32h7_spi_runtime_suspend,
-			   stm32h7_spi_runtime_resume, NULL)
-};
-
-static struct platform_driver stm32h7_spi_driver = {
-	.probe = stm32h7_spi_probe,
-	.remove = stm32h7_spi_remove,
-	.driver = {
-		.name = DRIVER_NAME,
-		.pm = &stm32h7_spi_pm_ops,
-		.of_match_table = stm32h7_spi_of_match,
-	},
-};
-
-module_platform_driver(stm32h7_spi_driver);
-
-MODULE_ALIAS("platform:" DRIVER_NAME);
-MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
-MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/spi/spi-stm32h7.c b/drivers/spi/spi-stm32h7.c
new file mode 100644
index 0000000..4ae3e94
--- /dev/null
+++ b/drivers/spi/spi-stm32h7.c
@@ -0,0 +1,1340 @@
+/*
+ * STMicroelectronics STM32H7 SPI Controller driver (master mode only)
+ *
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
+ *
+ * License terms: GPL V2.0.
+ *
+ * spi_stm32h7 driver is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * spi_stm32h7 driver is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * spi_stm32h7 driver. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/debugfs.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/spi/spi.h>
+
+#define DRIVER_NAME "spi_stm32h7"
+
+/* STM32H7 SPI registers */
+#define STM32H7_SPI_CR1			0x00
+#define STM32H7_SPI_CR2			0x04
+#define STM32H7_SPI_CFG1		0x08
+#define STM32H7_SPI_CFG2		0x0C
+#define STM32H7_SPI_IER			0x10
+#define STM32H7_SPI_SR			0x14
+#define STM32H7_SPI_IFCR		0x18
+#define STM32H7_SPI_TXDR		0x20
+#define STM32H7_SPI_RXDR		0x30
+#define STM32H7_SPI_I2SCFGR		0x50
+
+/* STM32H7_SPI_CR1 bit fields */
+#define STM32H7_SPI_CR1_SPE		BIT(0)
+#define STM32H7_SPI_CR1_MASRX		BIT(8)
+#define STM32H7_SPI_CR1_CSTART		BIT(9)
+#define STM32H7_SPI_CR1_CSUSP		BIT(10)
+#define STM32H7_SPI_CR1_HDDIR		BIT(11)
+#define STM32H7_SPI_CR1_SSI		BIT(12)
+
+/* STM32H7_SPI_CR2 bit fields */
+#define STM32H7_SPI_CR2_TSIZE_SHIFT	0
+#define STM32H7_SPI_CR2_TSIZE		GENMASK(15, 0)
+
+/* STM32H7_SPI_CFG1 bit fields */
+#define STM32H7_SPI_CFG1_DSIZE_SHIFT	0
+#define STM32H7_SPI_CFG1_DSIZE		GENMASK(4, 0)
+#define STM32H7_SPI_CFG1_FTHLV_SHIFT	5
+#define STM32H7_SPI_CFG1_FTHLV		GENMASK(8, 5)
+#define STM32H7_SPI_CFG1_RXDMAEN	BIT(14)
+#define STM32H7_SPI_CFG1_TXDMAEN	BIT(15)
+#define STM32H7_SPI_CFG1_MBR_SHIFT	28
+#define STM32H7_SPI_CFG1_MBR		GENMASK(30, 28)
+#define STM32H7_SPI_CFG1_MBR_MIN	0
+#define STM32H7_SPI_CFG1_MBR_MAX	(GENMASK(30, 28) >> 28)
+
+/* STM32H7_SPI_CFG2 bit fields */
+#define STM32H7_SPI_CFG2_MIDI_SHIFT	4
+#define STM32H7_SPI_CFG2_MIDI		GENMASK(7, 4)
+#define STM32H7_SPI_CFG2_COMM_SHIFT	17
+#define STM32H7_SPI_CFG2_COMM		GENMASK(18, 17)
+#define STM32H7_SPI_CFG2_SP_SHIFT	19
+#define STM32H7_SPI_CFG2_SP		GENMASK(21, 19)
+#define STM32H7_SPI_CFG2_MASTER		BIT(22)
+#define STM32H7_SPI_CFG2_LSBFRST	BIT(23)
+#define STM32H7_SPI_CFG2_CPHA		BIT(24)
+#define STM32H7_SPI_CFG2_CPOL		BIT(25)
+#define STM32H7_SPI_CFG2_SSM		BIT(26)
+#define STM32H7_SPI_CFG2_AFCNTR		BIT(31)
+
+/* STM32H7_SPI_IER bit fields */
+#define STM32H7_SPI_IER_RXPIE		BIT(0)
+#define STM32H7_SPI_IER_TXPIE		BIT(1)
+#define STM32H7_SPI_IER_DXPIE		BIT(2)
+#define STM32H7_SPI_IER_EOTIE		BIT(3)
+#define STM32H7_SPI_IER_TXTFIE		BIT(4)
+#define STM32H7_SPI_IER_OVRIE		BIT(6)
+#define STM32H7_SPI_IER_MODFIE		BIT(9)
+#define STM32H7_SPI_IER_ALL		GENMASK(10, 0)
+
+/* STM32H7_SPI_SR bit fields */
+#define STM32H7_SPI_SR_RXP		BIT(0)
+#define STM32H7_SPI_SR_TXP		BIT(1)
+#define STM32H7_SPI_SR_EOT		BIT(3)
+#define STM32H7_SPI_SR_OVR		BIT(6)
+#define STM32H7_SPI_SR_MODF		BIT(9)
+#define STM32H7_SPI_SR_SUSP		BIT(11)
+#define STM32H7_SPI_SR_RXPLVL_SHIFT	13
+#define STM32H7_SPI_SR_RXPLVL		GENMASK(14, 13)
+#define STM32H7_SPI_SR_RXWNE		BIT(15)
+
+/* STM32H7_SPI_IFCR bit fields */
+#define STM32H7_SPI_IFCR_ALL		GENMASK(11, 3)
+
+/* STM32H7_SPI_I2SCFGR bit fields */
+#define STM32H7_SPI_I2SCFGR_I2SMOD	BIT(0)
+
+/* STM32H7 SPI Master Baud Rate min/max divisor */
+#define STM32H7_SPI_MBR_DIV_MIN		(2 << STM32H7_SPI_CFG1_MBR_MIN)
+#define STM32H7_SPI_MBR_DIV_MAX		(2 << STM32H7_SPI_CFG1_MBR_MAX)
+
+/* STM32H7 SPI Communication mode */
+#define STM32H7_SPI_FULL_DUPLEX		0
+#define STM32H7_SPI_SIMPLEX_TX		1
+#define STM32H7_SPI_SIMPLEX_RX		2
+#define STM32H7_SPI_HALF_DUPLEX		3
+
+#define STM32H7_SPI_1HZ_NS		1000000000
+
+/**
+ * struct stm32h7_spi - private data of the SPI controller
+ * @dev: driver model representation of the controller
+ * @master: controller master interface
+ * @base: virtual memory area
+ * @clk: hw kernel clock feeding the SPI clock generator
+ * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
+ * @rst: SPI controller reset line
+ * @lock: prevent I/O concurrent access
+ * @irq: SPI controller interrupt line
+ * @fifo_size: size of the embedded fifo in bytes
+ * @cur_midi: master inter-data idleness in ns
+ * @cur_speed: speed configured in Hz
+ * @cur_bpw: number of bits in a single SPI data frame
+ * @cur_fthlv: fifo threshold level (data frames in a single data packet)
+ * @cur_comm: SPI communication mode
+ * @cur_xferlen: current transfer length in bytes
+ * @cur_usedma: boolean to know if dma is used in current transfer
+ * @tx_buf: data to be written, or NULL
+ * @rx_buf: data to be read, or NULL
+ * @tx_len: number of data to be written in bytes
+ * @rx_len: number of data to be read in bytes
+ * @dma_tx: dma channel for TX transfer
+ * @dma_rx: dma channel for RX transfer
+ * @phys_addr: SPI registers physical base address
+ */
+struct stm32h7_spi {
+	struct device *dev;
+	struct spi_master *master;
+	void __iomem *base;
+	struct clk *clk;
+	u32 clk_rate;
+	struct reset_control *rst;
+	spinlock_t lock; /* prevent I/O concurrent access */
+	int irq;
+	unsigned int fifo_size;
+
+	unsigned int cur_midi;
+	unsigned int cur_speed;
+	unsigned int cur_bpw;
+	unsigned int cur_fthlv;
+	unsigned int cur_comm;
+	unsigned int cur_xferlen;
+	bool cur_usedma;
+
+	const void *tx_buf;
+	void *rx_buf;
+	int tx_len;
+	int rx_len;
+	struct dma_chan *dma_tx;
+	struct dma_chan *dma_rx;
+	dma_addr_t phys_addr;
+};
+
+static inline void stm32h7_spi_set_bits(struct stm32h7_spi *spi,
+					u32 offset, u32 bits)
+{
+	writel_relaxed(readl_relaxed(spi->base + offset) | bits,
+		       spi->base + offset);
+}
+
+static inline void stm32h7_spi_clr_bits(struct stm32h7_spi *spi,
+					u32 offset, u32 bits)
+{
+	writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
+		       spi->base + offset);
+}
+
+/**
+ * stm32h7_spi_get_fifo_size - Return fifo size
+ * @spi: pointer to the spi controller data structure
+ */
+static int stm32h7_spi_get_fifo_size(struct stm32h7_spi *spi)
+{
+	unsigned long flags;
+	u32 count = 0;
+
+	spin_lock_irqsave(&spi->lock, flags);
+
+	stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
+
+	while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
+		writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
+
+	stm32h7_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
+
+	spin_unlock_irqrestore(&spi->lock, flags);
+
+	dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
+
+	return count;
+}
+
+/**
+ * stm32h7_spi_get_bpw_mask - Return bits per word mask
+ * @spi: pointer to the spi controller data structure
+ */
+static int stm32h7_spi_get_bpw_mask(struct stm32h7_spi *spi)
+{
+	unsigned long flags;
+	u32 cfg1, max_bpw;
+
+	spin_lock_irqsave(&spi->lock, flags);
+
+	/*
+	 * The most significant bit at DSIZE bit field is reserved when the
+	 * maximum data size of periperal instances is limited to 16-bit
+	 */
+	stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
+
+	cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
+	max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >>
+		  STM32H7_SPI_CFG1_DSIZE_SHIFT;
+	max_bpw += 1;
+
+	spin_unlock_irqrestore(&spi->lock, flags);
+
+	dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
+
+	return SPI_BPW_RANGE_MASK(4, max_bpw);
+}
+
+/**
+ * stm32h7_spi_prepare_mbr - Determine STM32H7_SPI_CFG1.MBR value
+ * @spi: pointer to the spi controller data structure
+ * @speed_hz: requested speed
+ *
+ * Return STM32H7_SPI_CFG1.MBR value in case of success or -EINVAL
+ */
+static int stm32h7_spi_prepare_mbr(struct stm32h7_spi *spi, u32 speed_hz)
+{
+	u32 div, mbrdiv;
+
+	div = DIV_ROUND_UP(spi->clk_rate, speed_hz);
+
+	/*
+	 * SPI framework set xfer->speed_hz to master->max_speed_hz if
+	 * xfer->speed_hz is greater than master->max_speed_hz, and it returns
+	 * an error when xfer->speed_hz is lower than master->min_speed_hz, so
+	 * no need to check it there.
+	 * However, we need to ensure the following calculations.
+	 */
+	if (div < STM32H7_SPI_MBR_DIV_MIN ||
+	    div > STM32H7_SPI_MBR_DIV_MAX)
+		return -EINVAL;
+
+	/* Determine the first power of 2 greater than or equal to div */
+	if (div & (div - 1))
+		mbrdiv = fls(div);
+	else
+		mbrdiv = fls(div) - 1;
+
+	spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
+
+	return mbrdiv - 1;
+}
+
+/**
+ * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
+ * @spi: pointer to the spi controller data structure
+ */
+static u32 stm32h7_spi_prepare_fthlv(struct stm32h7_spi *spi)
+{
+	u32 fthlv, half_fifo;
+
+	/* data packet should not exceed 1/2 of fifo space */
+	half_fifo = (spi->fifo_size / 2);
+
+	if (spi->cur_bpw <= 8)
+		fthlv = half_fifo;
+	else if (spi->cur_bpw <= 16)
+		fthlv = half_fifo / 2;
+	else
+		fthlv = half_fifo / 4;
+
+	/* align packet size with data registers access */
+	if (spi->cur_bpw > 8)
+		fthlv -= (fthlv % 2); /* multiple of 2 */
+	else
+		fthlv -= (fthlv % 4); /* multiple of 4 */
+
+	return fthlv;
+}
+
+/**
+ * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
+ * @spi: pointer to the spi controller data structure
+ *
+ * Read from tx_buf depends on remaining bytes to avoid to read beyond
+ * tx_buf end.
+ */
+static void stm32h7_spi_write_txfifo(struct stm32h7_spi *spi)
+{
+	while ((spi->tx_len > 0) &&
+	       (readl_relaxed(spi->base + STM32H7_SPI_SR) &
+		STM32H7_SPI_SR_TXP)) {
+		u32 offs = spi->cur_xferlen - spi->tx_len;
+
+		if (spi->tx_len >= sizeof(u32)) {
+			const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
+
+			writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
+			spi->tx_len -= sizeof(u32);
+		} else if (spi->tx_len >= sizeof(u16)) {
+			const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
+
+			writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
+			spi->tx_len -= sizeof(u16);
+		} else {
+			const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
+
+			writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
+			spi->tx_len -= sizeof(u8);
+		}
+	}
+
+	dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
+}
+
+/**
+ * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
+ * @spi: pointer to the spi controller data structure
+ *
+ * Write in rx_buf depends on remaining bytes to avoid to write beyond
+ * rx_buf end.
+ */
+static void stm32h7_spi_read_rxfifo(struct stm32h7_spi *spi, bool flush)
+{
+	u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
+	u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
+		     STM32H7_SPI_SR_RXPLVL_SHIFT;
+
+	while ((spi->rx_len > 0) &&
+	       ((sr & STM32H7_SPI_SR_RXP) ||
+		(flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
+		u32 offs = spi->cur_xferlen - spi->rx_len;
+
+		if ((spi->rx_len >= sizeof(u32)) ||
+		    (flush && (sr & STM32H7_SPI_SR_RXWNE))) {
+			u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
+
+			*rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
+			spi->rx_len -= sizeof(u32);
+		} else if ((spi->rx_len >= sizeof(u16)) ||
+			   (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) {
+			u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
+
+			*rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
+			spi->rx_len -= sizeof(u16);
+		} else {
+			u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
+
+			*rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
+			spi->rx_len -= sizeof(u8);
+		}
+
+		sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
+		rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
+			 STM32H7_SPI_SR_RXPLVL_SHIFT;
+	}
+
+	dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
+		flush ? "(flush)" : "", spi->rx_len);
+}
+
+/**
+ * stm32h7_spi_enable - Enable SPI controller
+ * @spi: pointer to the spi controller data structure
+ *
+ * SPI data transfer is enabled but spi_ker_ck is idle.
+ * STM32H7_SPI_CFG1 and STM32H7_SPI_CFG2 are now write protected.
+ */
+static void stm32h7_spi_enable(struct stm32h7_spi *spi)
+{
+	dev_dbg(spi->dev, "enable controller\n");
+
+	stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
+}
+
+/**
+ * stm32h7_spi_disable - Disable SPI controller
+ * @spi: pointer to the spi controller data structure
+ *
+ * RX-Fifo is flushed when SPI controller is disabled. To prevent any data
+ * loss, use stm32h7_spi_read_rxfifo(flush) to read the remaining bytes in
+ * RX-Fifo.
+ */
+static void stm32h7_spi_disable(struct stm32h7_spi *spi)
+{
+	unsigned long flags;
+	u32 cr1, sr;
+
+	dev_dbg(spi->dev, "disable controller\n");
+
+	spin_lock_irqsave(&spi->lock, flags);
+
+	cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
+
+	if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
+		spin_unlock_irqrestore(&spi->lock, flags);
+		return;
+	}
+
+	/* Wait on EOT or suspend the flow */
+	if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR,
+					      sr, !(sr & STM32H7_SPI_SR_EOT),
+					      10, 100000) < 0) {
+		if (cr1 & STM32H7_SPI_CR1_CSTART) {
+			writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP,
+				       spi->base + STM32H7_SPI_CR1);
+			if (readl_relaxed_poll_timeout_atomic(
+						spi->base + STM32H7_SPI_SR,
+						sr, !(sr & STM32H7_SPI_SR_SUSP),
+						10, 100000) < 0)
+				dev_warn(spi->dev,
+					 "Suspend request timeout\n");
+		}
+	}
+
+	if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0))
+		stm32h7_spi_read_rxfifo(spi, true);
+
+	if (spi->cur_usedma && spi->tx_buf)
+		dmaengine_terminate_all(spi->dma_tx);
+	if (spi->cur_usedma && spi->rx_buf)
+		dmaengine_terminate_all(spi->dma_rx);
+
+	stm32h7_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
+
+	stm32h7_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
+						    STM32H7_SPI_CFG1_RXDMAEN);
+
+	/* Disable interrupts and clear status flags */
+	writel_relaxed(0, spi->base + STM32H7_SPI_IER);
+	writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
+
+	spin_unlock_irqrestore(&spi->lock, flags);
+}
+
+/**
+ * stm32h7_spi_can_dma - Determine if the transfer is eligible for DMA use
+ *
+ * If the current transfer size is greater than fifo size, use DMA.
+ */
+static bool stm32h7_spi_can_dma(struct spi_master *master,
+				struct spi_device *spi_dev,
+				struct spi_transfer *transfer)
+{
+	struct stm32h7_spi *spi = spi_master_get_devdata(master);
+
+	dev_dbg(spi->dev, "%s: %s\n", __func__,
+		(transfer->len > spi->fifo_size) ? "true" : "false");
+
+	return (transfer->len > spi->fifo_size);
+}
+
+/**
+ * stm32h7_spi_irq - Interrupt handler for SPI controller events
+ * @irq: interrupt line
+ * @dev_id: SPI controller master interface
+ */
+static irqreturn_t stm32h7_spi_irq(int irq, void *dev_id)
+{
+	struct spi_master *master = dev_id;
+	struct stm32h7_spi *spi = spi_master_get_devdata(master);
+	u32 sr, ier, mask;
+	unsigned long flags;
+	bool end = false;
+
+	spin_lock_irqsave(&spi->lock, flags);
+
+	sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
+	ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
+
+	mask = ier;
+	/* EOTIE is triggered on EOT, SUSP and TXC events. */
+	mask |= STM32H7_SPI_SR_SUSP;
+	/*
+	 * When TXTF is set, DXPIE and TXPIE are cleared. So in case of
+	 * Full-Duplex, need to poll RXP event to know if there are remaining
+	 * data, before disabling SPI.
+	 */
+	if (spi->rx_buf && !spi->cur_usedma)
+		mask |= STM32H7_SPI_SR_RXP;
+
+	if (!(sr & mask)) {
+		dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
+			sr, ier);
+		spin_unlock_irqrestore(&spi->lock, flags);
+		return IRQ_NONE;
+	}
+
+	if (sr & STM32H7_SPI_SR_SUSP) {
+		dev_warn(spi->dev, "Communication suspended\n");
+		if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
+			stm32h7_spi_read_rxfifo(spi, false);
+		/*
+		 * If communication is suspended while using DMA, it means
+		 * that something went wrong, so stop the current transfer
+		 */
+		if (spi->cur_usedma)
+			end = true;
+	}
+
+	if (sr & STM32H7_SPI_SR_MODF) {
+		dev_warn(spi->dev, "Mode fault: transfer aborted\n");
+		end = true;
+	}
+
+	if (sr & STM32H7_SPI_SR_OVR) {
+		dev_warn(spi->dev, "Overrun: received value discarded\n");
+		if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
+			stm32h7_spi_read_rxfifo(spi, false);
+		/*
+		 * If overrun is detected while using DMA, it means that
+		 * something went wrong, so stop the current transfer
+		 */
+		if (spi->cur_usedma)
+			end = true;
+	}
+
+	if (sr & STM32H7_SPI_SR_EOT) {
+		if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
+			stm32h7_spi_read_rxfifo(spi, true);
+		end = true;
+	}
+
+	if (sr & STM32H7_SPI_SR_TXP)
+		if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
+			stm32h7_spi_write_txfifo(spi);
+
+	if (sr & STM32H7_SPI_SR_RXP)
+		if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
+			stm32h7_spi_read_rxfifo(spi, false);
+
+	writel_relaxed(mask, spi->base + STM32H7_SPI_IFCR);
+
+	spin_unlock_irqrestore(&spi->lock, flags);
+
+	if (end) {
+		spi_finalize_current_transfer(master);
+		stm32h7_spi_disable(spi);
+	}
+
+	return IRQ_HANDLED;
+}
+
+/**
+ * stm32h7_spi_setup - setup device chip select
+ */
+static int stm32h7_spi_setup(struct spi_device *spi_dev)
+{
+	int ret = 0;
+
+	if (!gpio_is_valid(spi_dev->cs_gpio)) {
+		dev_err(&spi_dev->dev, "%d is not a valid gpio\n",
+			spi_dev->cs_gpio);
+		return -EINVAL;
+	}
+
+	dev_dbg(&spi_dev->dev, "%s: set gpio%d output %s\n", __func__,
+		spi_dev->cs_gpio,
+		(spi_dev->mode & SPI_CS_HIGH) ? "low" : "high");
+
+	ret = gpio_direction_output(spi_dev->cs_gpio,
+				    !(spi_dev->mode & SPI_CS_HIGH));
+
+	return ret;
+}
+
+/**
+ * stm32h7_spi_prepare_msg - set up the controller to transfer a single message
+ */
+static int stm32h7_spi_prepare_msg(struct spi_master *master,
+				   struct spi_message *msg)
+{
+	struct stm32h7_spi *spi = spi_master_get_devdata(master);
+	struct spi_device *spi_dev = msg->spi;
+	struct device_node *np = spi_dev->dev.of_node;
+	unsigned long flags;
+	u32 cfg2_clrb = 0, cfg2_setb = 0;
+
+	/* SPI slave device may need time between data frames */
+	spi->cur_midi = 0;
+	if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
+		dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
+
+	if (spi_dev->mode & SPI_CPOL)
+		cfg2_setb |= STM32H7_SPI_CFG2_CPOL;
+	else
+		cfg2_clrb |= STM32H7_SPI_CFG2_CPOL;
+
+	if (spi_dev->mode & SPI_CPHA)
+		cfg2_setb |= STM32H7_SPI_CFG2_CPHA;
+	else
+		cfg2_clrb |= STM32H7_SPI_CFG2_CPHA;
+
+	if (spi_dev->mode & SPI_LSB_FIRST)
+		cfg2_setb |= STM32H7_SPI_CFG2_LSBFRST;
+	else
+		cfg2_clrb |= STM32H7_SPI_CFG2_LSBFRST;
+
+	dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
+		spi_dev->mode & SPI_CPOL,
+		spi_dev->mode & SPI_CPHA,
+		spi_dev->mode & SPI_LSB_FIRST,
+		spi_dev->mode & SPI_CS_HIGH);
+
+	spin_lock_irqsave(&spi->lock, flags);
+
+	if (cfg2_clrb || cfg2_setb)
+		writel_relaxed(
+			(readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
+				~cfg2_clrb) | cfg2_setb,
+			       spi->base + STM32H7_SPI_CFG2);
+
+	spin_unlock_irqrestore(&spi->lock, flags);
+
+	return 0;
+}
+
+/**
+ * stm32h7_spi_dma_cb - dma callback
+ *
+ * DMA callback is called when the transfer is complete or when an error
+ * occurs. If the transfer is complete, EOT flag is raised.
+ */
+static void stm32h7_spi_dma_cb(void *data)
+{
+	struct stm32h7_spi *spi = data;
+	unsigned long flags;
+	u32 sr;
+
+	spin_lock_irqsave(&spi->lock, flags);
+
+	sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
+
+	spin_unlock_irqrestore(&spi->lock, flags);
+
+	if (!(sr & STM32H7_SPI_SR_EOT))
+		dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr);
+
+	/* Now wait for EOT, or SUSP or OVR in case of error */
+}
+
+/**
+ * stm32h7_spi_dma_config - configure dma slave channel depending on current
+ *			    transfer bits_per_word.
+ */
+static void stm32h7_spi_dma_config(struct stm32h7_spi *spi,
+				   struct dma_slave_config *dma_conf,
+				   enum dma_transfer_direction dir)
+{
+	enum dma_slave_buswidth buswidth;
+	u32 maxburst;
+
+	if (spi->cur_bpw <= 8)
+		buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
+	else if (spi->cur_bpw <= 16)
+		buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
+	else
+		buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
+
+	/* Valid for DMA Half or Full Fifo threshold */
+	if (spi->cur_fthlv == 2)
+		maxburst = 1;
+	else
+		maxburst = spi->cur_fthlv;
+
+	memset(dma_conf, 0, sizeof(struct dma_slave_config));
+	dma_conf->direction = dir;
+	if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
+		dma_conf->src_addr = spi->phys_addr + STM32H7_SPI_RXDR;
+		dma_conf->src_addr_width = buswidth;
+		dma_conf->src_maxburst = maxburst;
+
+		dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
+			buswidth, maxburst);
+	} else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
+		dma_conf->dst_addr = spi->phys_addr + STM32H7_SPI_TXDR;
+		dma_conf->dst_addr_width = buswidth;
+		dma_conf->dst_maxburst = maxburst;
+
+		dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
+			buswidth, maxburst);
+	}
+}
+
+/**
+ * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
+ *				  interrupts
+ *
+ * It must returns 0 if the transfer is finished or 1 if the transfer is still
+ * in progress.
+ */
+static int stm32h7_spi_transfer_one_irq(struct stm32h7_spi *spi)
+{
+	unsigned long flags;
+	u32 ier = 0;
+
+	/* Enable the interrupts relative to the current communication mode */
+	if (spi->tx_buf && spi->rx_buf)	/* Full Duplex */
+		ier |= STM32H7_SPI_IER_DXPIE;
+	else if (spi->tx_buf)		/* Half-Duplex TX dir or Simplex TX */
+		ier |= STM32H7_SPI_IER_TXPIE;
+	else if (spi->rx_buf)		/* Half-Duplex RX dir or Simplex RX */
+		ier |= STM32H7_SPI_IER_RXPIE;
+
+	/* Enable the interrupts relative to the end of transfer */
+	ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
+	       STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
+
+	spin_lock_irqsave(&spi->lock, flags);
+
+	stm32h7_spi_enable(spi);
+
+	/* Be sure to have data in fifo before starting data transfer */
+	if (spi->tx_buf)
+		stm32h7_spi_write_txfifo(spi);
+
+	stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
+
+	writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
+
+	spin_unlock_irqrestore(&spi->lock, flags);
+
+	return 1;
+}
+
+/**
+ * stm32h7_spi_transfer_one_dma - transfer a single spi_transfer using DMA
+ *
+ * It must returns 0 if the transfer is finished or 1 if the transfer is still
+ * in progress.
+ */
+static int stm32h7_spi_transfer_one_dma(struct stm32h7_spi *spi,
+					struct spi_transfer *xfer)
+{
+	struct dma_slave_config tx_dma_conf, rx_dma_conf;
+	struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
+	unsigned long flags;
+	u32 ier = 0;
+
+	spin_lock_irqsave(&spi->lock, flags);
+
+	rx_dma_desc = NULL;
+	if (spi->rx_buf) {
+		stm32h7_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
+		dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
+
+		/* Enable Rx DMA request */
+		stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG1,
+				   STM32H7_SPI_CFG1_RXDMAEN);
+
+		rx_dma_desc = dmaengine_prep_slave_sg(
+					spi->dma_rx, xfer->rx_sg.sgl,
+					xfer->rx_sg.nents,
+					rx_dma_conf.direction,
+					DMA_PREP_INTERRUPT);
+	}
+
+	tx_dma_desc = NULL;
+	if (spi->tx_buf) {
+		stm32h7_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
+		dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
+
+		tx_dma_desc = dmaengine_prep_slave_sg(
+					spi->dma_tx, xfer->tx_sg.sgl,
+					xfer->tx_sg.nents,
+					tx_dma_conf.direction,
+					DMA_PREP_INTERRUPT);
+	}
+
+	if ((spi->tx_buf && !tx_dma_desc) ||
+	    (spi->rx_buf && !rx_dma_desc))
+		goto dma_desc_error;
+
+	if (rx_dma_desc) {
+		rx_dma_desc->callback = stm32h7_spi_dma_cb;
+		rx_dma_desc->callback_param = spi;
+
+		if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
+			dev_err(spi->dev, "Rx DMA submit failed\n");
+			goto dma_desc_error;
+		}
+		/* Enable Rx DMA channel */
+		dma_async_issue_pending(spi->dma_rx);
+	}
+
+	if (tx_dma_desc) {
+		if (spi->cur_comm == STM32H7_SPI_SIMPLEX_TX) {
+			tx_dma_desc->callback = stm32h7_spi_dma_cb;
+			tx_dma_desc->callback_param = spi;
+		}
+
+		if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
+			dev_err(spi->dev, "Tx DMA submit failed\n");
+			goto dma_submit_error;
+		}
+		/* Enable Tx DMA channel */
+		dma_async_issue_pending(spi->dma_tx);
+
+		/* Enable Tx DMA request */
+		stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG1,
+				     STM32H7_SPI_CFG1_TXDMAEN);
+	}
+
+	/* Enable the interrupts relative to the end of transfer */
+	ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
+	       STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
+	writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
+
+	stm32h7_spi_enable(spi);
+
+	stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
+
+	spin_unlock_irqrestore(&spi->lock, flags);
+
+	return 1;
+
+dma_submit_error:
+	if (spi->rx_buf)
+		dmaengine_terminate_all(spi->dma_rx);
+
+dma_desc_error:
+	stm32h7_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN);
+
+	spin_unlock_irqrestore(&spi->lock, flags);
+
+	dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
+
+	return stm32h7_spi_transfer_one_irq(spi);
+}
+
+/**
+ * stm32h7_spi_transfer_one_setup - common setup to transfer a single
+ *				    spi_transfer either using DMA or
+ *				    interrupts.
+ */
+static int stm32h7_spi_transfer_one_setup(struct stm32h7_spi *spi,
+					  struct spi_device *spi_dev,
+					  struct spi_transfer *transfer)
+{
+	unsigned long flags;
+	u32 cfg1_clrb = 0, cfg1_setb = 0, cfg2_clrb = 0, cfg2_setb = 0;
+	u32 mode, nb_words;
+	int ret = 0;
+
+	spin_lock_irqsave(&spi->lock, flags);
+
+	if (spi->cur_bpw != transfer->bits_per_word) {
+		u32 bpw, fthlv;
+
+		spi->cur_bpw = transfer->bits_per_word;
+		bpw = spi->cur_bpw - 1;
+
+		cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
+		cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
+			     STM32H7_SPI_CFG1_DSIZE;
+
+		spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi);
+		fthlv = spi->cur_fthlv - 1;
+
+		cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
+		cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
+			     STM32H7_SPI_CFG1_FTHLV;
+	}
+
+	if (spi->cur_speed != transfer->speed_hz) {
+		int mbr;
+
+		/* Update spi->cur_speed with real clock speed */
+		mbr = stm32h7_spi_prepare_mbr(spi, transfer->speed_hz);
+		if (mbr < 0) {
+			ret = mbr;
+			goto out;
+		}
+
+		transfer->speed_hz = spi->cur_speed;
+
+		cfg1_clrb |= STM32H7_SPI_CFG1_MBR;
+		cfg1_setb |= ((u32)mbr << STM32H7_SPI_CFG1_MBR_SHIFT) &
+			     STM32H7_SPI_CFG1_MBR;
+	}
+
+	if (cfg1_clrb || cfg1_setb)
+		writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
+				~cfg1_clrb) | cfg1_setb,
+			       spi->base + STM32H7_SPI_CFG1);
+
+	mode = STM32H7_SPI_FULL_DUPLEX;
+	if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
+		/*
+		 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
+		 * is forbidden und unvalidated by SPI subsystem so depending
+		 * on the valid buffer, we can determine the direction of the
+		 * transfer.
+		 */
+		mode = STM32H7_SPI_HALF_DUPLEX;
+		if (!transfer->tx_buf)
+			stm32h7_spi_clr_bits(spi, STM32H7_SPI_CR1,
+					     STM32H7_SPI_CR1_HDDIR);
+		else if (!transfer->rx_buf)
+			stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1,
+					     STM32H7_SPI_CR1_HDDIR);
+	} else {
+		if (!transfer->tx_buf)
+			mode = STM32H7_SPI_SIMPLEX_RX;
+		else if (!transfer->rx_buf)
+			mode = STM32H7_SPI_SIMPLEX_TX;
+	}
+	if (spi->cur_comm != mode) {
+		spi->cur_comm = mode;
+
+		cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
+		cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) &
+			     STM32H7_SPI_CFG2_COMM;
+	}
+
+	cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
+	if ((transfer->len > 1) && (spi->cur_midi > 0)) {
+		u32 sck_period_ns = DIV_ROUND_UP(STM32H7_SPI_1HZ_NS,
+						 spi->cur_speed);
+		u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
+			       (u32)STM32H7_SPI_CFG2_MIDI >>
+			       STM32H7_SPI_CFG2_MIDI_SHIFT);
+
+		dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
+			sck_period_ns, midi, midi * sck_period_ns);
+
+		cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) &
+			     STM32H7_SPI_CFG2_MIDI;
+	}
+
+	if (cfg2_clrb || cfg2_setb)
+		writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
+				~cfg2_clrb) | cfg2_setb,
+			       spi->base + STM32H7_SPI_CFG2);
+
+	if (spi->cur_bpw <= 8)
+		nb_words = transfer->len;
+	else if (spi->cur_bpw <= 16)
+		nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
+	else
+		nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
+	nb_words <<= STM32H7_SPI_CR2_TSIZE_SHIFT;
+
+	if (nb_words <= STM32H7_SPI_CR2_TSIZE) {
+		writel_relaxed(nb_words, spi->base + STM32H7_SPI_CR2);
+	} else {
+		ret = -EMSGSIZE;
+		goto out;
+	}
+
+	spi->cur_xferlen = transfer->len;
+
+	dev_dbg(spi->dev, "transfer communication mode set to %d\n",
+		spi->cur_comm);
+	dev_dbg(spi->dev,
+		"data frame of %d-bit, data packet of %d data frames\n",
+		spi->cur_bpw, spi->cur_fthlv);
+	dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
+	dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
+		spi->cur_xferlen, nb_words);
+	dev_dbg(spi->dev, "dma %s\n",
+		(spi->cur_usedma) ? "enabled" : "disabled");
+
+out:
+	spin_unlock_irqrestore(&spi->lock, flags);
+
+	return ret;
+}
+
+/**
+ * stm32h7_spi_transfer_one - transfer a single spi_transfer
+ *
+ * It must return 0 if the transfer is finished or 1 if the transfer is still
+ * in progress.
+ */
+static int stm32h7_spi_transfer_one(struct spi_master *master,
+				    struct spi_device *spi_dev,
+				    struct spi_transfer *transfer)
+{
+	struct stm32h7_spi *spi = spi_master_get_devdata(master);
+	int ret;
+
+	spi->tx_buf = transfer->tx_buf;
+	spi->rx_buf = transfer->rx_buf;
+	spi->tx_len = spi->tx_buf ? transfer->len : 0;
+	spi->rx_len = spi->rx_buf ? transfer->len : 0;
+
+	spi->cur_usedma = (master->can_dma &&
+			   stm32h7_spi_can_dma(master, spi_dev, transfer));
+
+	ret = stm32h7_spi_transfer_one_setup(spi, spi_dev, transfer);
+	if (ret) {
+		dev_err(spi->dev, "SPI transfer setup failed\n");
+		return ret;
+	}
+
+	if (spi->cur_usedma)
+		return stm32h7_spi_transfer_one_dma(spi, transfer);
+	else
+		return stm32h7_spi_transfer_one_irq(spi);
+}
+
+/**
+ * stm32h7_spi_unprepare_msg - relax the hardware
+ *
+ * Normally, if TSIZE has been configured, we should relax the hardware at the
+ * reception of the EOT interrupt. But in case of error, EOT will not be
+ * raised. So the subsystem unprepare_message call allows us to properly
+ * complete the transfer from an hardware point of view.
+ */
+static int stm32h7_spi_unprepare_msg(struct spi_master *master,
+				     struct spi_message *msg)
+{
+	struct stm32h7_spi *spi = spi_master_get_devdata(master);
+
+	stm32h7_spi_disable(spi);
+
+	return 0;
+}
+
+/**
+ * stm32h7_spi_config - Configure SPI controller as SPI master
+ */
+static int stm32h7_spi_config(struct stm32h7_spi *spi)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&spi->lock, flags);
+
+	/* Ensure I2SMOD bit is kept cleared */
+	stm32h7_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
+			     STM32H7_SPI_I2SCFGR_I2SMOD);
+
+	/*
+	 * - SS input value high
+	 * - transmitter half duplex direction
+	 * - automatic communication suspend when RX-Fifo is full
+	 */
+	stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI |
+						   STM32H7_SPI_CR1_HDDIR |
+						   STM32H7_SPI_CR1_MASRX);
+
+	/*
+	 * - Set the master mode (default Motorola mode)
+	 * - Consider 1 master/n slaves configuration and
+	 *   SS input value is determined by the SSI bit
+	 * - keep control of all associated GPIOs
+	 */
+	stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER |
+						    STM32H7_SPI_CFG2_SSM |
+						    STM32H7_SPI_CFG2_AFCNTR);
+
+	spin_unlock_irqrestore(&spi->lock, flags);
+
+	return 0;
+}
+
+static const struct of_device_id stm32h7_spi_of_match[] = {
+	{ .compatible = "st,stm32h7-spi", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, stm32h7_spi_of_match);
+
+static int stm32h7_spi_probe(struct platform_device *pdev)
+{
+	struct spi_master *master;
+	struct stm32h7_spi *spi;
+	struct resource *res;
+	int i, ret;
+
+	master = spi_alloc_master(&pdev->dev, sizeof(struct stm32h7_spi));
+	if (!master) {
+		dev_err(&pdev->dev, "spi master allocation failed\n");
+		return -ENOMEM;
+	}
+	platform_set_drvdata(pdev, master);
+
+	spi = spi_master_get_devdata(master);
+	spi->dev = &pdev->dev;
+	spi->master = master;
+	spin_lock_init(&spi->lock);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	spi->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(spi->base)) {
+		ret = PTR_ERR(spi->base);
+		goto err_master_put;
+	}
+	spi->phys_addr = (dma_addr_t)res->start;
+
+	spi->irq = platform_get_irq(pdev, 0);
+	if (spi->irq <= 0) {
+		dev_err(&pdev->dev, "no irq: %d\n", spi->irq);
+		ret = -ENOENT;
+		goto err_master_put;
+	}
+	ret = devm_request_threaded_irq(&pdev->dev, spi->irq, NULL,
+					stm32h7_spi_irq, IRQF_ONESHOT,
+					pdev->name, master);
+	if (ret) {
+		dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
+			ret);
+		goto err_master_put;
+	}
+
+	spi->clk = devm_clk_get(&pdev->dev, 0);
+	if (IS_ERR(spi->clk)) {
+		ret = PTR_ERR(spi->clk);
+		dev_err(&pdev->dev, "clk get failed: %d\n", ret);
+		goto err_master_put;
+	}
+
+	ret = clk_prepare_enable(spi->clk);
+	if (ret) {
+		dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
+		goto err_master_put;
+	}
+	spi->clk_rate = clk_get_rate(spi->clk);
+	if (!spi->clk_rate) {
+		dev_err(&pdev->dev, "clk rate = 0\n");
+		ret = -EINVAL;
+		goto err_clk_disable;
+	}
+
+	spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+	if (!IS_ERR(spi->rst)) {
+		reset_control_assert(spi->rst);
+		udelay(2);
+		reset_control_deassert(spi->rst);
+	}
+
+	spi->fifo_size = stm32h7_spi_get_fifo_size(spi);
+
+	ret = stm32h7_spi_config(spi);
+	if (ret) {
+		dev_err(&pdev->dev, "controller configuration failed: %d\n",
+			ret);
+		goto err_clk_disable;
+	}
+
+	master->dev.of_node = pdev->dev.of_node;
+	master->auto_runtime_pm = true;
+	master->bus_num = pdev->id;
+	master->mode_bits = SPI_MODE_3 | SPI_CS_HIGH | SPI_LSB_FIRST |
+			    SPI_3WIRE | SPI_LOOP;
+	master->bits_per_word_mask = stm32h7_spi_get_bpw_mask(spi);
+	master->max_speed_hz = spi->clk_rate / STM32H7_SPI_MBR_DIV_MIN;
+	master->min_speed_hz = spi->clk_rate / STM32H7_SPI_MBR_DIV_MAX;
+	master->setup = stm32h7_spi_setup;
+	master->prepare_message = stm32h7_spi_prepare_msg;
+	master->transfer_one = stm32h7_spi_transfer_one;
+	master->unprepare_message = stm32h7_spi_unprepare_msg;
+
+	spi->dma_tx = dma_request_slave_channel(spi->dev, "tx");
+	if (!spi->dma_tx)
+		dev_warn(&pdev->dev, "failed to request tx dma channel\n");
+	else
+		master->dma_tx = spi->dma_tx;
+
+	spi->dma_rx = dma_request_slave_channel(spi->dev, "rx");
+	if (!spi->dma_rx)
+		dev_warn(&pdev->dev, "failed to request rx dma channel\n");
+	else
+		master->dma_rx = spi->dma_rx;
+
+	if (spi->dma_tx || spi->dma_rx)
+		master->can_dma = stm32h7_spi_can_dma;
+
+	pm_runtime_set_active(&pdev->dev);
+	pm_runtime_enable(&pdev->dev);
+
+	ret = devm_spi_register_master(&pdev->dev, master);
+	if (ret) {
+		dev_err(&pdev->dev, "spi master registration failed: %d\n",
+			ret);
+		goto err_dma_release;
+	}
+
+	if (!master->cs_gpios) {
+		dev_err(&pdev->dev, "no CS gpios available\n");
+		ret = -EINVAL;
+		goto err_dma_release;
+	}
+
+	for (i = 0; i < master->num_chipselect; i++) {
+		if (!gpio_is_valid(master->cs_gpios[i])) {
+			dev_err(&pdev->dev, "%i is not a valid gpio\n",
+				master->cs_gpios[i]);
+			ret = -EINVAL;
+			goto err_dma_release;
+		}
+
+		ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
+					DRIVER_NAME);
+		if (ret) {
+			dev_err(&pdev->dev, "can't get CS gpio %i\n",
+				master->cs_gpios[i]);
+			goto err_dma_release;
+		}
+	}
+
+	dev_info(&pdev->dev, "driver initialized\n");
+
+	return 0;
+
+err_dma_release:
+	if (spi->dma_tx)
+		dma_release_channel(spi->dma_tx);
+	if (spi->dma_rx)
+		dma_release_channel(spi->dma_rx);
+
+	pm_runtime_disable(&pdev->dev);
+err_clk_disable:
+	clk_disable_unprepare(spi->clk);
+err_master_put:
+	spi_master_put(master);
+
+	return ret;
+}
+
+static int stm32h7_spi_remove(struct platform_device *pdev)
+{
+	struct spi_master *master = platform_get_drvdata(pdev);
+	struct stm32h7_spi *spi = spi_master_get_devdata(master);
+
+	stm32h7_spi_disable(spi);
+
+	if (master->dma_tx)
+		dma_release_channel(master->dma_tx);
+	if (master->dma_rx)
+		dma_release_channel(master->dma_rx);
+
+	clk_disable_unprepare(spi->clk);
+
+	pm_runtime_disable(&pdev->dev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int stm32h7_spi_runtime_suspend(struct device *dev)
+{
+	struct spi_master *master = dev_get_drvdata(dev);
+	struct stm32h7_spi *spi = spi_master_get_devdata(master);
+
+	clk_disable_unprepare(spi->clk);
+
+	return 0;
+}
+
+static int stm32h7_spi_runtime_resume(struct device *dev)
+{
+	struct spi_master *master = dev_get_drvdata(dev);
+	struct stm32h7_spi *spi = spi_master_get_devdata(master);
+
+	return clk_prepare_enable(spi->clk);
+}
+#endif
+
+#ifdef CONFIG_PM_SLEEP
+static int stm32h7_spi_suspend(struct device *dev)
+{
+	struct spi_master *master = dev_get_drvdata(dev);
+	int ret;
+
+	ret = spi_master_suspend(master);
+	if (ret)
+		return ret;
+
+	return pm_runtime_force_suspend(dev);
+}
+
+static int stm32h7_spi_resume(struct device *dev)
+{
+	struct spi_master *master = dev_get_drvdata(dev);
+	struct stm32h7_spi *spi = spi_master_get_devdata(master);
+	int ret;
+
+	ret = pm_runtime_force_resume(dev);
+	if (ret)
+		return ret;
+
+	ret = spi_master_resume(master);
+	if (ret)
+		clk_disable_unprepare(spi->clk);
+
+	return ret;
+}
+#endif
+
+static const struct dev_pm_ops stm32h7_spi_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(stm32h7_spi_suspend, stm32h7_spi_resume)
+	SET_RUNTIME_PM_OPS(stm32h7_spi_runtime_suspend,
+			   stm32h7_spi_runtime_resume, NULL)
+};
+
+static struct platform_driver stm32h7_spi_driver = {
+	.probe = stm32h7_spi_probe,
+	.remove = stm32h7_spi_remove,
+	.driver = {
+		.name = DRIVER_NAME,
+		.pm = &stm32h7_spi_pm_ops,
+		.of_match_table = stm32h7_spi_of_match,
+	},
+};
+
+module_platform_driver(stm32h7_spi_driver);
+
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_DESCRIPTION("STMicroelectronics STM32H7 SPI Controller driver");
+MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
+MODULE_LICENSE("GPL v2");
-- 
2.7.4

[PATCH 3/5] spi: stm32: add driver for STM32F4 controller

[cezary.gapinski]

From: Cezary Gapinski <cezary.gapinski@gmail.com>

The STM32F4 Serial Peripheral Interface (SPI) can be used to communicate
with external devices while using the specific synchronous protocol. This
version supports full-duplex communication  with 8 or 16-bit per word.
DMA capability is optionally supported when RX and TX DMA channels are
enabled at the same time for transfer longer than 16 bytes.
Now only master mode can be used.

Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com>
---
 drivers/spi/Kconfig       |   10 +
 drivers/spi/Makefile      |    1 +
 drivers/spi/spi-stm32f4.c | 1002 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 1013 insertions(+)
 create mode 100644 drivers/spi/spi-stm32f4.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 0151334..fc40616 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -655,6 +655,16 @@ config SPI_STM32H7
 	  is not available, the driver automatically falls back to
 	  PIO mode.
 
+config SPI_STM32F4
+	tristate "STMicroelectronics STM32F4 SPI controller"
+	depends on ARCH_STM32 || COMPILE_TEST
+	help
+	  SPI driver for STMicroelectronics STM32F4 SoCs.
+
+	  STM32F4 SPI controller supports DMA and PIO modes. When DMA
+	  is not available, the driver automatically falls back to
+	  PIO mode.
+
 config SPI_STM32_QSPI
 	tristate "STMicroelectronics STM32 QUAD SPI controller"
 	depends on ARCH_STM32 || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 6f24938..3fb0f98 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -94,6 +94,7 @@ obj-$(CONFIG_SPI_SIRF)		+= spi-sirf.o
 obj-$(CONFIG_SPI_SLAVE_MT27XX)          += spi-slave-mt27xx.o
 obj-$(CONFIG_SPI_SPRD)			+= spi-sprd.o
 obj-$(CONFIG_SPI_SPRD_ADI)		+= spi-sprd-adi.o
+obj-$(CONFIG_SPI_STM32F4) 		+= spi-stm32f4.o
 obj-$(CONFIG_SPI_STM32H7) 		+= spi-stm32h7.o
 obj-$(CONFIG_SPI_STM32_QSPI) 		+= spi-stm32-qspi.o
 obj-$(CONFIG_SPI_ST_SSC4)		+= spi-st-ssc4.o
diff --git a/drivers/spi/spi-stm32f4.c b/drivers/spi/spi-stm32f4.c
new file mode 100644
index 0000000..755222b
--- /dev/null
+++ b/drivers/spi/spi-stm32f4.c
@@ -0,0 +1,1002 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// STMicroelectronics STM32F4 SPI Controller driver (master mode only)
+//
+// Author(s): Cezary Gapinski <cezary.gapinski@gmail.com>
+//
+// This driver is based on spi-stm32h7.c
+
+#include <linux/debugfs.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/spi/spi.h>
+
+#define DRIVER_NAME "spi_stm32f4"
+
+/* STM32F4 SPI registers */
+#define STM32F4_SPI_CR1			0x00
+#define STM32F4_SPI_CR2			0x04
+#define STM32F4_SPI_SR			0x08
+#define STM32F4_SPI_DR			0x0C
+#define STM32F4_SPI_I2SCFGR		0x1C
+
+/* STM32F4_SPI_CR1 bit fields */
+#define STM32F4_SPI_CR1_CPHA		BIT(0)
+#define STM32F4_SPI_CR1_CPOL		BIT(1)
+#define STM32F4_SPI_CR1_MSTR		BIT(2)
+#define STM32F4_SPI_CR1_BR_SHIFT	3
+#define STM32F4_SPI_CR1_BR		GENMASK(5, 3)
+#define STM32F4_SPI_CR1_SPE		BIT(6)
+#define STM32F4_SPI_CR1_LSBFRST		BIT(7)
+#define STM32F4_SPI_CR1_SSI		BIT(8)
+#define STM32F4_SPI_CR1_SSM		BIT(9)
+#define STM32F4_SPI_CR1_RXONLY		BIT(10)
+#define STM32F4_SPI_CR1_DFF		BIT(11)
+#define STM32F4_SPI_CR1_CRCNEXT		BIT(12)
+#define STM32F4_SPI_CR1_CRCEN		BIT(13)
+#define STM32F4_SPI_CR1_BIDIOE		BIT(14)
+#define STM32F4_SPI_CR1_BIDIMODE	BIT(15)
+#define STM32F4_SPI_CR1_BR_MIN		0
+#define STM32F4_SPI_CR1_BR_MAX		(GENMASK(5, 3) >> 3)
+
+/* STM32F4_SPI_CR2 bit fields */
+#define STM32F4_SPI_CR2_RXDMAEN		BIT(0)
+#define STM32F4_SPI_CR2_TXDMAEN		BIT(1)
+#define STM32F4_SPI_CR2_SSOE		BIT(2)
+#define STM32F4_SPI_CR2_FRF		BIT(4)
+#define STM32F4_SPI_CR2_ERRIE		BIT(5)
+#define STM32F4_SPI_CR2_RXNEIE		BIT(6)
+#define STM32F4_SPI_CR2_TXEIE		BIT(7)
+
+/* STM32F4_SPI_SR bit fields */
+#define STM32F4_SPI_SR_RXNE		BIT(0)
+#define STM32F4_SPI_SR_TXE		BIT(1)
+#define STM32F4_SPI_SR_CHSIDE		BIT(2)
+#define STM32F4_SPI_SR_UDR		BIT(3)
+#define STM32F4_SPI_SR_CRCERR		BIT(4)
+#define STM32F4_SPI_SR_MODF		BIT(5)
+#define STM32F4_SPI_SR_OVR		BIT(6)
+#define STM32F4_SPI_SR_BSY		BIT(7)
+#define STM32F4_SPI_SR_FRE		BIT(8)
+
+/* STM32F4_SPI_I2SCFGR bit fields */
+#define STM32F4_SPI_I2SCFGR_I2SMOD	BIT(11)
+
+/* STM32F4 SPI Baud Rate min/max divisor */
+#define STM32F4_SPI_BR_DIV_MIN		(2 << STM32F4_SPI_CR1_BR_MIN)
+#define STM32F4_SPI_BR_DIV_MAX		(2 << STM32F4_SPI_CR1_BR_MAX)
+
+/* use PIO for small transfers, avoiding DMA setup/teardown overhead */
+#define STM32F4_DMA_MIN_BYTES		16
+
+/**
+ * struct stm32f4_spi - private data of the SPI controller
+ * @dev: driver model representation of the controller
+ * @master: controller master interface
+ * @base: virtual memory area
+ * @clk: hw kernel clock feeding the SPI clock generator
+ * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
+ * @rst: SPI controller reset line
+ * @lock: prevent I/O concurrent access
+ * @irq: SPI controller interrupt line
+ * @cur_speed: speed configured in Hz
+ * @cur_bpw: number of bits in a single SPI data frame
+ * @cur_xferlen: current transfer length in bytes
+ * @cur_usedma: boolean to know if dma is used in current transfer
+ * @tx_buf: data to be written, or NULL
+ * @rx_buf: data to be read, or NULL
+ * @tx_len: number of data to be written in bytes
+ * @rx_len: number of data to be read in bytes
+ * @phys_addr: SPI registers physical base address
+ */
+struct stm32f4_spi {
+	struct device *dev;
+	struct spi_master *master;
+	void __iomem *base;
+	struct clk *clk;
+	u32 clk_rate;
+	struct reset_control *rst;
+	spinlock_t lock;
+	int irq;
+
+	unsigned int cur_speed;
+	unsigned int cur_bpw;
+	unsigned int cur_xferlen;
+	bool cur_usedma;
+
+	const void *tx_buf;
+	void *rx_buf;
+	int tx_len;
+	int rx_len;
+	dma_addr_t phys_addr;
+};
+
+static inline void stm32f4_spi_set_bits(struct stm32f4_spi *spi,
+					u32 offset, u32 bits)
+{
+	writel_relaxed(readl_relaxed(spi->base + offset) | bits,
+		       spi->base + offset);
+}
+
+static inline void stm32f4_spi_clr_bits(struct stm32f4_spi *spi,
+					u32 offset, u32 bits)
+{
+	writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
+		       spi->base + offset);
+}
+
+/**
+ * stm32f4_spi_prepare_mbr - Determine STM32F4_SPI_CR1.BR value
+ * @spi: pointer to the spi controller data structure
+ * @speed_hz: requested speed
+ *
+ * Return STM32F4_SPI_CR1.BR value in case of success or -EINVAL
+ */
+static int stm32f4_spi_prepare_mbr(struct stm32f4_spi *spi, u32 speed_hz)
+{
+	u32 div, mbrdiv;
+
+	div = DIV_ROUND_UP(spi->clk_rate, speed_hz);
+
+	/*
+	 * SPI framework set xfer->speed_hz to master->max_speed_hz if
+	 * xfer->speed_hz is greater than master->max_speed_hz, and it returns
+	 * an error when xfer->speed_hz is lower than master->min_speed_hz, so
+	 * no need to check it there.
+	 * However, we need to ensure the following calculations.
+	 */
+	if (div < STM32F4_SPI_BR_DIV_MIN ||
+	    div > STM32F4_SPI_BR_DIV_MAX)
+		return -EINVAL;
+
+	/* Determine the first power of 2 greater than or equal to div */
+	if (div & (div - 1))
+		mbrdiv = fls(div);
+	else
+		mbrdiv = fls(div) - 1;
+
+	spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
+
+	return mbrdiv - 1;
+}
+
+/**
+ * stm32f4_spi_write_tx - Write bytes to Data Register
+ * @spi: pointer to the spi controller data structure
+ *
+ * Read from tx_buf depends on remaining bytes to avoid to read beyond
+ * tx_buf end.
+ */
+static void stm32f4_spi_write_tx(struct stm32f4_spi *spi)
+{
+	if (spi->tx_len > 0) {
+		u32 offs = spi->cur_xferlen - spi->tx_len;
+
+		if (spi->cur_bpw == 16) {
+			const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
+
+			writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR);
+			spi->tx_len -= sizeof(u16);
+		} else {
+			const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
+
+			writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR);
+			spi->tx_len -= sizeof(u8);
+		}
+	}
+
+	dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
+}
+
+/**
+ * stm32f4_spi_read_rx - Read bytes from Data Register
+ * @spi: pointer to the spi controller data structure
+ *
+ * Write in rx_buf depends on remaining bytes to avoid to write beyond
+ * rx_buf end.
+ */
+static void stm32f4_spi_read_rx(struct stm32f4_spi *spi)
+{
+	if (spi->rx_len > 0) {
+		u32 offs = spi->cur_xferlen - spi->rx_len;
+
+		if (spi->cur_bpw == 16) {
+			u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
+
+			*rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR);
+			spi->rx_len -= sizeof(u16);
+		} else {
+			u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
+
+			*rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR);
+			spi->rx_len -= sizeof(u8);
+		}
+	}
+
+	dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
+}
+
+/**
+ * stm32f4_spi_enable - Enable SPI controller
+ * @spi: pointer to the spi controller data structure
+ */
+static void stm32f4_spi_enable(struct stm32f4_spi *spi)
+{
+	dev_dbg(spi->dev, "enable controller\n");
+
+	stm32f4_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
+}
+
+/**
+ * stm32f4_spi_disable - Disable SPI controller
+ * @spi: pointer to the spi controller data structure
+ */
+static void stm32f4_spi_disable(struct stm32f4_spi *spi)
+{
+	unsigned long flags;
+	struct spi_master *master = spi->master;
+
+	dev_dbg(spi->dev, "disable controller\n");
+
+	spin_lock_irqsave(&spi->lock, flags);
+
+	stm32f4_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
+
+	if (spi->cur_usedma) {
+		dmaengine_terminate_all(master->dma_tx);
+		dmaengine_terminate_all(master->dma_rx);
+	}
+
+	stm32f4_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN |
+						   STM32F4_SPI_CR2_RXDMAEN);
+
+	/* Disable interrupts */
+	stm32f4_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXNEIE |
+						   STM32F4_SPI_CR2_ERRIE);
+	/* Sequence to clear OVR flag */
+	readl_relaxed(spi->base + STM32F4_SPI_DR);
+	readl_relaxed(spi->base + STM32F4_SPI_SR);
+
+	spin_unlock_irqrestore(&spi->lock, flags);
+}
+
+/**
+ * stm32f4_spi_can_dma - Determine if the transfer is eligible for DMA use
+ *
+ * If the current transfer size is greater than defined size, use DMA.
+ */
+static bool stm32f4_spi_can_dma(struct spi_master *master,
+				struct spi_device *spi_dev,
+				struct spi_transfer *transfer)
+{
+	struct stm32f4_spi *spi = spi_master_get_devdata(master);
+
+	dev_dbg(spi->dev, "%s: %s\n", __func__,
+		(transfer->len > STM32F4_DMA_MIN_BYTES) ? "true" : "false");
+
+	return (transfer->len > STM32F4_DMA_MIN_BYTES);
+}
+
+/**
+ * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
+ * @irq: interrupt line
+ * @dev_id: SPI controller master interface
+ */
+static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
+{
+	struct spi_master *master = dev_id;
+	struct stm32f4_spi *spi = spi_master_get_devdata(master);
+	u32 sr, mask;
+	unsigned long flags;
+	bool end = false;
+
+	spin_lock_irqsave(&spi->lock, flags);
+
+	sr = readl_relaxed(spi->base + STM32F4_SPI_SR);
+	/*
+	 * BSY flag is not handled in interrupt
+	 * TXE flag is set and is handled when RXNE flag occurs
+	 */
+	sr &= ~(STM32F4_SPI_SR_BSY | STM32F4_SPI_SR_TXE);
+
+	mask = STM32F4_SPI_SR_RXNE;
+	if (spi->cur_usedma)
+		mask |= STM32F4_SPI_SR_OVR;
+
+	if (!(sr & mask)) {
+		dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
+		spin_unlock_irqrestore(&spi->lock, flags);
+		return IRQ_NONE;
+	}
+
+	if (sr & STM32F4_SPI_SR_OVR) {
+		dev_warn(spi->dev, "Overrun: received value discarded\n");
+
+		/* Sequence to clear OVR flag */
+		readl_relaxed(spi->base + STM32F4_SPI_DR);
+		readl_relaxed(spi->base + STM32F4_SPI_SR);
+
+		/*
+		 * If overrun is detected, it means that something went wrong,
+		 * so stop the current transfer. For interrupt transfer for
+		 * current configuration it should newer occurs. If it is
+		 * detected for DMA stop transfer.
+		 */
+		end = true;
+		goto end_irq;
+	}
+
+	stm32f4_spi_read_rx(spi);
+	if (spi->rx_len == 0)
+		end = true;
+	else
+		stm32f4_spi_write_tx(spi);
+
+end_irq:
+	spin_unlock_irqrestore(&spi->lock, flags);
+
+	if (end)
+		return IRQ_WAKE_THREAD;
+
+	return IRQ_HANDLED;
+}
+
+/**
+ * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
+ * @irq: interrupt line
+ * @dev_id: SPI controller master interface
+ */
+static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id)
+{
+	struct spi_master *master = dev_id;
+	struct stm32f4_spi *spi = spi_master_get_devdata(master);
+
+	spi_finalize_current_transfer(master);
+	stm32f4_spi_disable(spi);
+
+	return IRQ_HANDLED;
+}
+
+/**
+ * stm32f4_spi_setup - setup device chip select
+ */
+static int stm32f4_spi_setup(struct spi_device *spi_dev)
+{
+	int ret = 0;
+
+	if (!gpio_is_valid(spi_dev->cs_gpio)) {
+		dev_err(&spi_dev->dev, "%d is not a valid gpio\n",
+			spi_dev->cs_gpio);
+		return -EINVAL;
+	}
+
+	dev_dbg(&spi_dev->dev, "%s: set gpio%d output %s\n", __func__,
+		spi_dev->cs_gpio,
+		(spi_dev->mode & SPI_CS_HIGH) ? "low" : "high");
+
+	ret = gpio_direction_output(spi_dev->cs_gpio,
+				    !(spi_dev->mode & SPI_CS_HIGH));
+
+	return ret;
+}
+
+/**
+ * stm32f4_spi_prepare_msg - set up the controller to transfer a single message
+ */
+static int stm32f4_spi_prepare_msg(struct spi_master *master,
+				   struct spi_message *msg)
+{
+	struct stm32f4_spi *spi = spi_master_get_devdata(master);
+	struct spi_device *spi_dev = msg->spi;
+	unsigned long flags;
+	u32 cr1_clrb = 0, cr1_setb = 0;
+
+	if (spi_dev->mode & SPI_CPOL)
+		cr1_setb |= STM32F4_SPI_CR1_CPOL;
+	else
+		cr1_clrb |= STM32F4_SPI_CR1_CPOL;
+
+	if (spi_dev->mode & SPI_CPHA)
+		cr1_setb |= STM32F4_SPI_CR1_CPHA;
+	else
+		cr1_clrb |= STM32F4_SPI_CR1_CPHA;
+
+	if (spi_dev->mode & SPI_LSB_FIRST)
+		cr1_setb |= STM32F4_SPI_CR1_LSBFRST;
+	else
+		cr1_clrb |= STM32F4_SPI_CR1_LSBFRST;
+
+	dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
+		spi_dev->mode & SPI_CPOL,
+		spi_dev->mode & SPI_CPHA,
+		spi_dev->mode & SPI_LSB_FIRST,
+		spi_dev->mode & SPI_CS_HIGH);
+
+	spin_lock_irqsave(&spi->lock, flags);
+
+	if (cr1_clrb || cr1_setb)
+		writel_relaxed((readl_relaxed(spi->base + STM32F4_SPI_CR1) &
+				~cr1_clrb) | cr1_setb,
+			       spi->base + STM32F4_SPI_CR1);
+
+	spin_unlock_irqrestore(&spi->lock, flags);
+
+	return 0;
+}
+
+/**
+ * stm32f4_spi_dma_rx_cb - DMA callback
+ *
+ * DMA callback is called when the transfer is complete for receiving mode.
+ */
+static void stm32f4_spi_dma_rx_cb(void *data)
+{
+	struct spi_master *master = data;
+	struct stm32f4_spi *spi = spi_master_get_devdata(master);
+
+	spi_finalize_current_transfer(master);
+	stm32f4_spi_disable(spi);
+}
+
+/**
+ * stm32f4_spi_dma_config - configure DMA slave channel depending on current
+ *			    transfer bits_per_word.
+ */
+static void stm32f4_spi_dma_config(struct stm32f4_spi *spi,
+				   struct dma_slave_config *dma_conf,
+				   enum dma_transfer_direction dir)
+{
+	enum dma_slave_buswidth buswidth;
+
+	if (spi->cur_bpw == 16)
+		buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
+	else
+		buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
+
+	memset(dma_conf, 0, sizeof(struct dma_slave_config));
+	dma_conf->direction = dir;
+	if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
+		dma_conf->src_addr = spi->phys_addr + STM32F4_SPI_DR;
+		dma_conf->src_addr_width = buswidth;
+
+		dev_dbg(spi->dev, "Rx DMA config buswidth=%d\n", buswidth);
+	} else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
+		dma_conf->dst_addr = spi->phys_addr + STM32F4_SPI_DR;
+		dma_conf->dst_addr_width = buswidth;
+
+		dev_dbg(spi->dev, "Tx DMA config buswidth=%d\n", buswidth);
+	}
+}
+
+/**
+ * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using
+ *				  interrupts
+ *
+ * It must returns 0 if the transfer is finished or 1 if the transfer is still
+ * in progress.
+ */
+static int stm32f4_spi_transfer_one_irq(struct stm32f4_spi *spi)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&spi->lock, flags);
+
+	stm32f4_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXNEIE |
+						   STM32F4_SPI_CR2_ERRIE);
+	stm32f4_spi_enable(spi);
+	stm32f4_spi_write_tx(spi);
+
+	spin_unlock_irqrestore(&spi->lock, flags);
+
+	return 1;
+}
+
+/**
+ * stm32f4_spi_transfer_one_dma - transfer a single spi_transfer using DMA
+ *
+ * It must returns 0 if the transfer is finished or 1 if the transfer is still
+ * in progress.
+ */
+static int stm32f4_spi_transfer_one_dma(struct stm32f4_spi *spi,
+					struct spi_transfer *xfer)
+{
+	struct dma_slave_config tx_dma_conf, rx_dma_conf;
+	struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
+	unsigned long flags;
+	struct spi_master *master = spi->master;
+
+	spin_lock_irqsave(&spi->lock, flags);
+
+	rx_dma_desc = NULL;
+	stm32f4_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
+	dmaengine_slave_config(master->dma_rx, &rx_dma_conf);
+
+	/* Enable Rx DMA request */
+	stm32f4_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN);
+
+	rx_dma_desc = dmaengine_prep_slave_sg(
+				master->dma_rx, xfer->rx_sg.sgl,
+				xfer->rx_sg.nents,
+				rx_dma_conf.direction,
+				DMA_PREP_INTERRUPT);
+
+	tx_dma_desc = NULL;
+	stm32f4_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
+	dmaengine_slave_config(master->dma_tx, &tx_dma_conf);
+
+	tx_dma_desc = dmaengine_prep_slave_sg(
+				master->dma_tx, xfer->tx_sg.sgl,
+				xfer->tx_sg.nents,
+				tx_dma_conf.direction,
+				DMA_PREP_INTERRUPT);
+
+	if (!tx_dma_desc || !rx_dma_desc)
+		goto dma_desc_error;
+
+	rx_dma_desc->callback = stm32f4_spi_dma_rx_cb;
+	rx_dma_desc->callback_param = spi->master;
+
+	if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
+		dev_err(spi->dev, "Rx DMA submit failed\n");
+		goto dma_desc_error;
+	}
+	/* Enable Rx DMA channel */
+	dma_async_issue_pending(master->dma_rx);
+
+	if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
+		dev_err(spi->dev, "Tx DMA submit failed\n");
+		goto dma_submit_error;
+	}
+	/* Enable Tx DMA channel */
+	dma_async_issue_pending(master->dma_tx);
+
+	/* Enable Tx DMA request */
+	stm32f4_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN);
+
+	/*
+	 * End of transfer will be handled in DMA RX Callback.
+	 * Enable the interrupts to detect OVR flag
+	 */
+	stm32f4_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE);
+
+	stm32f4_spi_enable(spi);
+
+	spin_unlock_irqrestore(&spi->lock, flags);
+
+	return 1;
+
+dma_submit_error:
+	dmaengine_terminate_all(master->dma_rx);
+
+dma_desc_error:
+	stm32f4_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN);
+
+	spin_unlock_irqrestore(&spi->lock, flags);
+
+	dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
+
+	return stm32f4_spi_transfer_one_irq(spi);
+}
+
+/**
+ * stm32f4_spi_transfer_one_setup - common setup to transfer a single
+ *				    spi_transfer either using DMA or
+ *				    interrupts.
+ */
+static int stm32f4_spi_transfer_one_setup(struct stm32f4_spi *spi,
+					  struct spi_device *spi_dev,
+					  struct spi_transfer *transfer)
+{
+	unsigned long flags;
+	u32 cr1_clrb = 0, cr1_setb = 0;
+	u32 nb_words;
+	int ret = 0;
+
+	spin_lock_irqsave(&spi->lock, flags);
+
+	if (spi->cur_bpw != transfer->bits_per_word) {
+		spi->cur_bpw = transfer->bits_per_word;
+		nb_words = spi->cur_bpw;
+		cr1_clrb |= STM32F4_SPI_CR1_DFF;
+
+		if (spi->cur_bpw == 16)
+			cr1_setb |= STM32F4_SPI_CR1_DFF;
+	}
+
+	if (spi->cur_speed != transfer->speed_hz) {
+		int mbr;
+
+		/* Update spi->cur_speed with real clock speed */
+		mbr = stm32f4_spi_prepare_mbr(spi, transfer->speed_hz);
+		if (mbr < 0) {
+			ret = mbr;
+			goto out;
+		}
+
+		transfer->speed_hz = spi->cur_speed;
+
+		cr1_clrb |= STM32F4_SPI_CR1_BR;
+		cr1_setb |= ((u32)mbr << STM32F4_SPI_CR1_BR_SHIFT) &
+			     STM32F4_SPI_CR1_BR;
+	}
+
+	if (cr1_clrb || cr1_setb)
+		writel_relaxed((readl_relaxed(spi->base + STM32F4_SPI_CR1) &
+				~cr1_clrb) | cr1_setb,
+			       spi->base + STM32F4_SPI_CR1);
+
+	spi->cur_xferlen = transfer->len;
+
+	dev_dbg(spi->dev, "full-duplex communication mode\n");
+	dev_dbg(spi->dev, "data frame of %d-bit\n", spi->cur_bpw);
+	dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
+	dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
+		spi->cur_xferlen, nb_words);
+	dev_dbg(spi->dev, "dma %s\n",
+		(spi->cur_usedma) ? "enabled" : "disabled");
+
+out:
+	spin_unlock_irqrestore(&spi->lock, flags);
+
+	return ret;
+}
+
+/**
+ * stm32f4_spi_transfer_one - transfer a single spi_transfer
+ *
+ * It must return 0 if the transfer is finished or 1 if the transfer is still
+ * in progress.
+ */
+static int stm32f4_spi_transfer_one(struct spi_master *master,
+				    struct spi_device *spi_dev,
+				    struct spi_transfer *transfer)
+{
+	struct stm32f4_spi *spi = spi_master_get_devdata(master);
+	int ret;
+
+	spi->tx_buf = transfer->tx_buf;
+	spi->rx_buf = transfer->rx_buf;
+	spi->tx_len = spi->tx_buf ? transfer->len : 0;
+	spi->rx_len = spi->rx_buf ? transfer->len : 0;
+
+	spi->cur_usedma = (master->can_dma &&
+			   stm32f4_spi_can_dma(master, spi_dev, transfer));
+
+	ret = stm32f4_spi_transfer_one_setup(spi, spi_dev, transfer);
+	if (ret) {
+		dev_err(spi->dev, "SPI transfer setup failed\n");
+		return ret;
+	}
+
+	if (spi->cur_usedma)
+		return stm32f4_spi_transfer_one_dma(spi, transfer);
+	else
+		return stm32f4_spi_transfer_one_irq(spi);
+}
+
+/**
+ * stm32f4_spi_unprepare_msg - relax the hardware
+ */
+static int stm32f4_spi_unprepare_msg(struct spi_master *master,
+				     struct spi_message *msg)
+{
+	struct stm32f4_spi *spi = spi_master_get_devdata(master);
+
+	stm32f4_spi_disable(spi);
+
+	return 0;
+}
+
+/**
+ * stm32f4_spi_config - configure SPI controller as SPI master
+ */
+static int stm32f4_spi_config(struct stm32f4_spi *spi)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&spi->lock, flags);
+
+	/* Ensure I2SMOD bit is kept cleared */
+	stm32f4_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR,
+			     STM32F4_SPI_I2SCFGR_I2SMOD);
+
+	/*
+	 * - SS input value high
+	 * - Set the master mode (default Motorola mode)
+	 * - Consider 1 master/n slaves configuration and
+	 *   SS input value is determined by the SSI bit
+	 */
+	stm32f4_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI |
+						   STM32F4_SPI_CR1_MSTR |
+						   STM32F4_SPI_CR1_SSM);
+
+	spin_unlock_irqrestore(&spi->lock, flags);
+
+	return 0;
+}
+
+/**
+ * stm32f4_release_dma - release DMA tx and rx channels
+ */
+static void stm32f4_release_dma(struct spi_master *master)
+{
+	if (master->dma_tx)
+		dma_release_channel(master->dma_tx);
+	if (master->dma_rx)
+		dma_release_channel(master->dma_rx);
+}
+
+/**
+ * stm32f4_spi_dma_prep - prepare controller to use DMA tx and rx channels
+ */
+static int stm32f4_spi_dma_prep(struct stm32f4_spi *spi,  struct device *dev)
+{
+	struct spi_master *master = spi->master;
+
+	master->dma_tx = dma_request_slave_channel(spi->dev, "tx");
+	if (!master->dma_tx) {
+		dev_warn(dev, "failed to request tx dma channel\n");
+		return -ENODEV;
+	}
+
+	master->dma_rx = dma_request_slave_channel(spi->dev, "rx");
+	if (!master->dma_rx) {
+		dev_warn(dev, "failed to request rx dma channel\n");
+		stm32f4_release_dma(master);
+		return -ENODEV;
+	}
+
+	master->can_dma = stm32f4_spi_can_dma;
+	dev_info(dev, "DMA available");
+	return 0;
+}
+
+static const struct of_device_id stm32f4_spi_of_match[] = {
+	{ .compatible = "st,stm32f4-spi", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, stm32f4_spi_of_match);
+
+static int stm32f4_spi_probe(struct platform_device *pdev)
+{
+	struct spi_master *master;
+	struct stm32f4_spi *spi;
+	struct resource *res;
+	int i, ret;
+
+	master = spi_alloc_master(&pdev->dev, sizeof(struct stm32f4_spi));
+	if (!master) {
+		dev_err(&pdev->dev, "spi master allocation failed\n");
+		return -ENOMEM;
+	}
+	platform_set_drvdata(pdev, master);
+
+	spi = spi_master_get_devdata(master);
+	spi->dev = &pdev->dev;
+	spi->master = master;
+	spin_lock_init(&spi->lock);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	spi->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(spi->base)) {
+		ret = PTR_ERR(spi->base);
+		goto err_master_put;
+	}
+	spi->phys_addr = (dma_addr_t)res->start;
+
+	spi->irq = platform_get_irq(pdev, 0);
+	if (spi->irq <= 0) {
+		dev_err(&pdev->dev, "no irq: %d\n", spi->irq);
+		ret = -ENOENT;
+		goto err_master_put;
+	}
+	ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
+					stm32f4_spi_irq_event,
+					stm32f4_spi_irq_thread,
+					IRQF_ONESHOT, pdev->name, master);
+	if (ret) {
+		dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
+			ret);
+		goto err_master_put;
+	}
+
+	spi->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(spi->clk)) {
+		ret = PTR_ERR(spi->clk);
+		dev_err(&pdev->dev, "clk get failed: %d\n", ret);
+		goto err_master_put;
+	}
+
+	ret = clk_prepare_enable(spi->clk);
+	if (ret) {
+		dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
+		goto err_master_put;
+	}
+	spi->clk_rate = clk_get_rate(spi->clk);
+	if (!spi->clk_rate) {
+		dev_err(&pdev->dev, "clk rate = 0\n");
+		ret = -EINVAL;
+		goto err_clk_disable;
+	}
+
+	spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+	if (!IS_ERR(spi->rst)) {
+		reset_control_assert(spi->rst);
+		udelay(2);
+		reset_control_deassert(spi->rst);
+	}
+
+	ret = stm32f4_spi_config(spi);
+	if (ret) {
+		dev_err(&pdev->dev, "controller configuration failed: %d\n",
+			ret);
+		goto err_clk_disable;
+	}
+
+	master->dev.of_node = pdev->dev.of_node;
+	master->auto_runtime_pm = true;
+	master->bus_num = pdev->id;
+	master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST;
+	master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
+	master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
+	master->max_speed_hz = spi->clk_rate / STM32F4_SPI_BR_DIV_MIN;
+	master->min_speed_hz = spi->clk_rate / STM32F4_SPI_BR_DIV_MAX;
+	master->setup = stm32f4_spi_setup;
+	master->prepare_message = stm32f4_spi_prepare_msg;
+	master->transfer_one = stm32f4_spi_transfer_one;
+	master->unprepare_message = stm32f4_spi_unprepare_msg;
+
+	/* optional DMA support */
+	ret = stm32f4_spi_dma_prep(spi, &pdev->dev);
+	if (ret < 0)
+		dev_warn(&pdev->dev, "DMA not available, using PIO mode\n");
+
+	pm_runtime_set_active(&pdev->dev);
+	pm_runtime_enable(&pdev->dev);
+
+	ret = devm_spi_register_master(&pdev->dev, master);
+	if (ret) {
+		dev_err(&pdev->dev, "spi master registration failed: %d\n",
+			ret);
+		goto err_dma_release;
+	}
+
+	if (!master->cs_gpios) {
+		dev_err(&pdev->dev, "no CS gpios available\n");
+		ret = -EINVAL;
+		goto err_dma_release;
+	}
+
+	for (i = 0; i < master->num_chipselect; i++) {
+		if (!gpio_is_valid(master->cs_gpios[i])) {
+			dev_err(&pdev->dev, "%i is not a valid gpio\n",
+				master->cs_gpios[i]);
+			ret = -EINVAL;
+			goto err_dma_release;
+		}
+
+		ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
+					DRIVER_NAME);
+		if (ret) {
+			dev_err(&pdev->dev, "can't get CS gpio %i\n",
+				master->cs_gpios[i]);
+			goto err_dma_release;
+		}
+	}
+
+	dev_info(&pdev->dev, "driver initialized\n");
+
+	return 0;
+
+err_dma_release:
+	stm32f4_release_dma(master);
+
+	pm_runtime_disable(&pdev->dev);
+err_clk_disable:
+	clk_disable_unprepare(spi->clk);
+err_master_put:
+	spi_master_put(master);
+
+	return ret;
+}
+
+static int stm32f4_spi_remove(struct platform_device *pdev)
+{
+	struct spi_master *master = platform_get_drvdata(pdev);
+	struct stm32f4_spi *spi = spi_master_get_devdata(master);
+
+	stm32f4_spi_disable(spi);
+
+	if (master->dma_tx)
+		dma_release_channel(master->dma_tx);
+	if (master->dma_rx)
+		dma_release_channel(master->dma_rx);
+
+	clk_disable_unprepare(spi->clk);
+
+	pm_runtime_disable(&pdev->dev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int stm32f4_spi_runtime_suspend(struct device *dev)
+{
+	struct spi_master *master = dev_get_drvdata(dev);
+	struct stm32f4_spi *spi = spi_master_get_devdata(master);
+
+	clk_disable_unprepare(spi->clk);
+
+	return 0;
+}
+
+static int stm32f4_spi_runtime_resume(struct device *dev)
+{
+	struct spi_master *master = dev_get_drvdata(dev);
+	struct stm32f4_spi *spi = spi_master_get_devdata(master);
+
+	return clk_prepare_enable(spi->clk);
+}
+#endif
+
+#ifdef CONFIG_PM_SLEEP
+static int stm32f4_spi_suspend(struct device *dev)
+{
+	struct spi_master *master = dev_get_drvdata(dev);
+	int ret;
+
+	ret = spi_master_suspend(master);
+	if (ret)
+		return ret;
+
+	return pm_runtime_force_suspend(dev);
+}
+
+static int stm32f4_spi_resume(struct device *dev)
+{
+	struct spi_master *master = dev_get_drvdata(dev);
+	struct stm32f4_spi *spi = spi_master_get_devdata(master);
+	int ret;
+
+	ret = pm_runtime_force_resume(dev);
+	if (ret)
+		return ret;
+
+	ret = spi_master_resume(master);
+	if (ret)
+		clk_disable_unprepare(spi->clk);
+
+	return ret;
+}
+#endif
+
+static const struct dev_pm_ops stm32f4_spi_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(stm32f4_spi_suspend, stm32f4_spi_resume)
+	SET_RUNTIME_PM_OPS(stm32f4_spi_runtime_suspend,
+			   stm32f4_spi_runtime_resume, NULL)
+};
+
+static struct platform_driver stm32f4_spi_driver = {
+	.probe = stm32f4_spi_probe,
+	.remove = stm32f4_spi_remove,
+	.driver = {
+		.name = DRIVER_NAME,
+		.pm = &stm32f4_spi_pm_ops,
+		.of_match_table = stm32f4_spi_of_match,
+	},
+};
+
+module_platform_driver(stm32f4_spi_driver);
+
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_DESCRIPTION("STMicroelectronics STM32F4 SPI Controller driver");
+MODULE_AUTHOR("Cezary Gapinski <cezary.gapinski@gmail.com>");
+MODULE_LICENSE("GPL v2");
-- 
2.7.4

[PATCH 4/5] ARM: dts: stm32: add SPI support on STM32F429 SoC

[cezary.gapinski]

From: Cezary Gapinski <cezary.gapinski@gmail.com>

This patch adds all SPI instances of the STM32F429 SoC.

Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com>
---
 arch/arm/boot/dts/stm32f429.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 8d6f028..8dbec00 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -314,6 +314,26 @@
 			status = "disabled";
 		};
 
+		spi2: spi@40003800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32f4-spi";
+			reg = <0x40003800 0x400>;
+			interrupts = <36>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
+			status = "disabled";
+		};
+
+		spi3: spi@40003C00 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32f4-spi";
+			reg = <0x40003C00 0x400>;
+			interrupts = <51>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
+			status = "disabled";
+		};
+
 		usart2: serial@40004400 {
 			compatible = "st,stm32-uart";
 			reg = <0x40004400 0x400>;
@@ -523,6 +543,26 @@
 			status = "disabled";
 		};
 
+		spi1: spi@40013000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32f4-spi";
+			reg = <0x40013000 0x400>;
+			interrupts = <35>;
+			clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
+			status = "disabled";
+		};
+
+		spi4: spi@40013400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32f4-spi";
+			reg = <0x40013400 0x400>;
+			interrupts = <84>;
+			clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
+			status = "disabled";
+		};
+
 		syscfg: system-config@40013800 {
 			compatible = "syscon";
 			reg = <0x40013800 0x400>;
@@ -587,6 +627,26 @@
 			};
 		};
 
+		spi5: spi@40015000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32f4-spi";
+			reg = <0x40015000 0x400>;
+			interrupts = <85>;
+			clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
+			status = "disabled";
+		};
+
+		spi6: spi@40015400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32f4-spi";
+			reg = <0x40015400 0x400>;
+			interrupts = <86>;
+			clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
+			status = "disabled";
+		};
+
 		pwrcfg: power-config@40007000 {
 			compatible = "syscon";
 			reg = <0x40007000 0x400>;
-- 
2.7.4

Re: [PATCH 4/5] ARM: dts: stm32: add SPI support on STM32F429 SoC

[Alexandre Torgue]

Hi Cezary,

On 12/9/18 2:53 PM, cezary.gapinski@gmail.com wrote:
> From: Cezary Gapinski <cezary.gapinski@gmail.com>
> 
> This patch adds all SPI instances of the STM32F429 SoC.
> 
> Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com>
> ---
>   arch/arm/boot/dts/stm32f429.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 60 insertions(+)
> 

Applied on stm32-next.

Thanks.
Alex

[PATCH 5/5] spi: stm32: add description about STM32F4 bindings

[cezary.gapinski]

From: Cezary Gapinski <cezary.gapinski@gmail.com>

Add description that STM32F4 can be used in compatible property.
Master Inter-Data Idleness optional property cannot be used in STM32F4.

Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com>
---
 Documentation/devicetree/bindings/spi/spi-stm32.txt | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-stm32.txt b/Documentation/devicetree/bindings/spi/spi-stm32.txt
index 1b3fa2c1..d82755c 100644
--- a/Documentation/devicetree/bindings/spi/spi-stm32.txt
+++ b/Documentation/devicetree/bindings/spi/spi-stm32.txt
@@ -7,7 +7,9 @@ from 4 to 32-bit data size. Although it can be configured as master or slave,
 only master is supported by the driver.
 
 Required properties:
-- compatible: Must be "st,stm32h7-spi".
+- compatible: Should be one of:
+  "st,stm32h7-spi"
+  "st,stm32f4-spi"
 - reg: Offset and length of the device's register set.
 - interrupts: Must contain the interrupt id.
 - clocks: Must contain an entry for spiclk (which feeds the internal clock
@@ -30,8 +32,9 @@ Child nodes represent devices on the SPI bus
   See ../spi/spi-bus.txt
 
 Optional properties:
-- st,spi-midi-ns: (Master Inter-Data Idleness) minimum time delay in
-		  nanoseconds inserted between two consecutive data frames.
+- st,spi-midi-ns: Only for STM32H7, (Master Inter-Data Idleness) minimum time
+		  delay in nanoseconds inserted between two consecutive data
+		  frames.
 
 
 Example:
-- 
2.7.4

Re: [PATCH 5/5] spi: stm32: add description about STM32F4 bindings

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 16332 bytes --]

Hi Cezary,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on spi/for-next]
[also build test WARNING on v4.20-rc6 next-20181214]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/cezary-gapinski-gmail-com/spi-stm32-rename-STM32-SPI-registers-and-functions-to-STM32H7/20181210-075839
base:   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
config: x86_64-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All warnings (new ones prefixed by >>):

>> drivers/spi/spi-stm32h7.c:1134:45: warning: Using plain integer as NULL pointer

vim +1134 drivers/spi/spi-stm32h7.c

dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1091  
52721092 drivers/spi/spi-stm32.c Cezary Gapinski    2018-12-09  1092  static int stm32h7_spi_probe(struct platform_device *pdev)
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1093  {
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1094  	struct spi_master *master;
52721092 drivers/spi/spi-stm32.c Cezary Gapinski    2018-12-09  1095  	struct stm32h7_spi *spi;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1096  	struct resource *res;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1097  	int i, ret;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1098  
52721092 drivers/spi/spi-stm32.c Cezary Gapinski    2018-12-09  1099  	master = spi_alloc_master(&pdev->dev, sizeof(struct stm32h7_spi));
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1100  	if (!master) {
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1101  		dev_err(&pdev->dev, "spi master allocation failed\n");
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1102  		return -ENOMEM;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1103  	}
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1104  	platform_set_drvdata(pdev, master);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1105  
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1106  	spi = spi_master_get_devdata(master);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1107  	spi->dev = &pdev->dev;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1108  	spi->master = master;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1109  	spin_lock_init(&spi->lock);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1110  
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1111  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1112  	spi->base = devm_ioremap_resource(&pdev->dev, res);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1113  	if (IS_ERR(spi->base)) {
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1114  		ret = PTR_ERR(spi->base);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1115  		goto err_master_put;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1116  	}
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1117  	spi->phys_addr = (dma_addr_t)res->start;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1118  
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1119  	spi->irq = platform_get_irq(pdev, 0);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1120  	if (spi->irq <= 0) {
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1121  		dev_err(&pdev->dev, "no irq: %d\n", spi->irq);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1122  		ret = -ENOENT;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1123  		goto err_master_put;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1124  	}
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1125  	ret = devm_request_threaded_irq(&pdev->dev, spi->irq, NULL,
52721092 drivers/spi/spi-stm32.c Cezary Gapinski    2018-12-09  1126  					stm32h7_spi_irq, IRQF_ONESHOT,
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1127  					pdev->name, master);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1128  	if (ret) {
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1129  		dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1130  			ret);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1131  		goto err_master_put;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1132  	}
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1133  
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21 @1134  	spi->clk = devm_clk_get(&pdev->dev, 0);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1135  	if (IS_ERR(spi->clk)) {
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1136  		ret = PTR_ERR(spi->clk);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1137  		dev_err(&pdev->dev, "clk get failed: %d\n", ret);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1138  		goto err_master_put;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1139  	}
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1140  
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1141  	ret = clk_prepare_enable(spi->clk);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1142  	if (ret) {
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1143  		dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1144  		goto err_master_put;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1145  	}
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1146  	spi->clk_rate = clk_get_rate(spi->clk);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1147  	if (!spi->clk_rate) {
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1148  		dev_err(&pdev->dev, "clk rate = 0\n");
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1149  		ret = -EINVAL;
3dbb3eef drivers/spi/spi-stm32.c Alexey Khoroshilov 2018-03-30  1150  		goto err_clk_disable;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1151  	}
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1152  
d5e9a4a4 drivers/spi/spi-stm32.c Philipp Zabel      2017-07-19  1153  	spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1154  	if (!IS_ERR(spi->rst)) {
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1155  		reset_control_assert(spi->rst);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1156  		udelay(2);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1157  		reset_control_deassert(spi->rst);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1158  	}
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1159  
52721092 drivers/spi/spi-stm32.c Cezary Gapinski    2018-12-09  1160  	spi->fifo_size = stm32h7_spi_get_fifo_size(spi);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1161  
52721092 drivers/spi/spi-stm32.c Cezary Gapinski    2018-12-09  1162  	ret = stm32h7_spi_config(spi);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1163  	if (ret) {
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1164  		dev_err(&pdev->dev, "controller configuration failed: %d\n",
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1165  			ret);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1166  		goto err_clk_disable;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1167  	}
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1168  
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1169  	master->dev.of_node = pdev->dev.of_node;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1170  	master->auto_runtime_pm = true;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1171  	master->bus_num = pdev->id;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1172  	master->mode_bits = SPI_MODE_3 | SPI_CS_HIGH | SPI_LSB_FIRST |
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1173  			    SPI_3WIRE | SPI_LOOP;
52721092 drivers/spi/spi-stm32.c Cezary Gapinski    2018-12-09  1174  	master->bits_per_word_mask = stm32h7_spi_get_bpw_mask(spi);
52721092 drivers/spi/spi-stm32.c Cezary Gapinski    2018-12-09  1175  	master->max_speed_hz = spi->clk_rate / STM32H7_SPI_MBR_DIV_MIN;
52721092 drivers/spi/spi-stm32.c Cezary Gapinski    2018-12-09  1176  	master->min_speed_hz = spi->clk_rate / STM32H7_SPI_MBR_DIV_MAX;
52721092 drivers/spi/spi-stm32.c Cezary Gapinski    2018-12-09  1177  	master->setup = stm32h7_spi_setup;
52721092 drivers/spi/spi-stm32.c Cezary Gapinski    2018-12-09  1178  	master->prepare_message = stm32h7_spi_prepare_msg;
52721092 drivers/spi/spi-stm32.c Cezary Gapinski    2018-12-09  1179  	master->transfer_one = stm32h7_spi_transfer_one;
52721092 drivers/spi/spi-stm32.c Cezary Gapinski    2018-12-09  1180  	master->unprepare_message = stm32h7_spi_unprepare_msg;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1181  
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1182  	spi->dma_tx = dma_request_slave_channel(spi->dev, "tx");
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1183  	if (!spi->dma_tx)
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1184  		dev_warn(&pdev->dev, "failed to request tx dma channel\n");
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1185  	else
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1186  		master->dma_tx = spi->dma_tx;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1187  
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1188  	spi->dma_rx = dma_request_slave_channel(spi->dev, "rx");
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1189  	if (!spi->dma_rx)
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1190  		dev_warn(&pdev->dev, "failed to request rx dma channel\n");
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1191  	else
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1192  		master->dma_rx = spi->dma_rx;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1193  
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1194  	if (spi->dma_tx || spi->dma_rx)
52721092 drivers/spi/spi-stm32.c Cezary Gapinski    2018-12-09  1195  		master->can_dma = stm32h7_spi_can_dma;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1196  
038ac869 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-27  1197  	pm_runtime_set_active(&pdev->dev);
038ac869 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-27  1198  	pm_runtime_enable(&pdev->dev);
038ac869 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-27  1199  
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1200  	ret = devm_spi_register_master(&pdev->dev, master);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1201  	if (ret) {
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1202  		dev_err(&pdev->dev, "spi master registration failed: %d\n",
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1203  			ret);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1204  		goto err_dma_release;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1205  	}
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1206  
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1207  	if (!master->cs_gpios) {
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1208  		dev_err(&pdev->dev, "no CS gpios available\n");
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1209  		ret = -EINVAL;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1210  		goto err_dma_release;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1211  	}
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1212  
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1213  	for (i = 0; i < master->num_chipselect; i++) {
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1214  		if (!gpio_is_valid(master->cs_gpios[i])) {
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1215  			dev_err(&pdev->dev, "%i is not a valid gpio\n",
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1216  				master->cs_gpios[i]);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1217  			ret = -EINVAL;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1218  			goto err_dma_release;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1219  		}
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1220  
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1221  		ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1222  					DRIVER_NAME);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1223  		if (ret) {
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1224  			dev_err(&pdev->dev, "can't get CS gpio %i\n",
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1225  				master->cs_gpios[i]);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1226  			goto err_dma_release;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1227  		}
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1228  	}
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1229  
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1230  	dev_info(&pdev->dev, "driver initialized\n");
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1231  
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1232  	return 0;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1233  
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1234  err_dma_release:
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1235  	if (spi->dma_tx)
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1236  		dma_release_channel(spi->dma_tx);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1237  	if (spi->dma_rx)
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1238  		dma_release_channel(spi->dma_rx);
038ac869 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-27  1239  
038ac869 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-27  1240  	pm_runtime_disable(&pdev->dev);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1241  err_clk_disable:
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1242  	clk_disable_unprepare(spi->clk);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1243  err_master_put:
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1244  	spi_master_put(master);
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1245  
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1246  	return ret;
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1247  }
dcbe0d84 drivers/spi/spi-stm32.c Amelie Delaunay    2017-06-21  1248  

:::::: The code at line 1134 was first introduced by commit
:::::: dcbe0d84dfa5a3e72b8e6ce622cd5ac78abbcab8 spi: add driver for STM32 SPI controller

:::::: TO: Amelie Delaunay <amelie.delaunay@st.com>
:::::: CC: Mark Brown <broonie@kernel.org>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 66659 bytes --]

Re: [PATCH 5/5] spi: stm32: add description about STM32F4 bindings

[Rob Herring]

On Sun,  9 Dec 2018 14:53:56 +0100, cezary.gapinski@gmail.com wrote:
> From: Cezary Gapinski <cezary.gapinski@gmail.com>
> 
> Add description that STM32F4 can be used in compatible property.
> Master Inter-Data Idleness optional property cannot be used in STM32F4.
> 
> Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com>
> ---
>  Documentation/devicetree/bindings/spi/spi-stm32.txt | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 0/5] Add support for STM32F4 SPI

[Amelie DELAUNAY]

Hi Cezary,

On 12/9/18 2:53 PM, cezary.gapinski@gmail.com wrote:
> From: Cezary Gapinski <cezary.gapinski@gmail.com>
> 
> This series of patches adds support for first generation of SPI interface
> for STM32F4 family.
> 

First of all, thanks for adding STM32F4 SPI support.

> This version of driver is mostly different to STM32H7 one. Based on linux
> kernel I2C drivers for STM32 where drivers were splited into STM32F4 and
> STM32F7 family the same approach seems to be sufficient for SPI STM32
> drivers. Therefore STM32H7 driver was moved to spi-stm32h7.c file and
> register and functions were renamed to be more specific to STM32H7.
> 

You're right, STM32F4 SPI is slightly different from STM32H7 one: 
register map/bits offsets are different and STM32H7 has an RX and TX FIFO.
But if you have a look on STM32F7 SPI [1], you'll see that STM32F7 SPI 
is based on STM32F4 SPI with new features (data frames & FIFOs) also 
available on STM32H7 SPI.

That's why STM32H7 SPI driver was called spi-stm32. The goal was to use 
compatible & match data to differentiate each STM32Fx specificities.

You can have a look on how it is managed in drivers/rtc/rtc-stm32.c (the 
same driver covers 2 HW version of STM32 RTC), or in 
drivers/iio/dac/stm32-dac-core.c and stm32-dac.c (the same driver also 
covers 2 HW version of STM32 DAC).

As your spi-stm32f4.c file is highly based on the existing spi-stm32.c 
file, I think that common code could be factored and specificities could 
be handled with compatible and match data.

Regards,
Amelie


[1] 
https://www.st.com/content/ccc/resource/technical/document/reference_manual/c5/cf/ef/52/c0/f1/4b/fa/DM00124865.pdf/files/DM00124865.pdf/jcr:content/translations/en.DM00124865.pdf

> For current version master mode with full-duplex and 8/16 bit data frame
> format are supported. There is no TX and RX FIFOs like in STM32H7.
> DMA capabilility is supported for messages longer than arbitrary number
> of bytes (that is set already to 16 bytes) when TX and RX channels are
> set at the same time.
> 
> Cezary Gapinski (5):
>    spi: stm32: rename STM32 SPI registers and functions to STM32H7
>    spi: stm32: rename spi-stm32 to spi-stm32h7
>    spi: stm32: add driver for STM32F4 controller
>    ARM: dts: stm32: add SPI support on STM32F429 SoC
>    spi: stm32: add description about STM32F4 bindings
> 
>   .../devicetree/bindings/spi/spi-stm32.txt          |    9 +-
>   arch/arm/boot/dts/stm32f429.dtsi                   |   60 +
>   drivers/spi/Kconfig                                |   18 +-
>   drivers/spi/Makefile                               |    3 +-
>   drivers/spi/spi-stm32.c                            | 1322 -------------------
>   drivers/spi/spi-stm32f4.c                          | 1002 +++++++++++++++
>   drivers/spi/spi-stm32h7.c                          | 1340 ++++++++++++++++++++
>   7 files changed, 2424 insertions(+), 1330 deletions(-)
>   delete mode 100644 drivers/spi/spi-stm32.c
>   create mode 100644 drivers/spi/spi-stm32f4.c
>   create mode 100644 drivers/spi/spi-stm32h7.c
>

Re: [PATCH 0/5] Add support for STM32F4 SPI

[Cezary Gapiński]

Hi Amelie,

On Mon, 2018-12-10 at 12:37 +0000, Amelie DELAUNAY wrote:
> Hi Cezary,
> 
> On 12/9/18 2:53 PM, cezary.gapinski@gmail.com wrote:
> > 
> > From: Cezary Gapinski <cezary.gapinski@gmail.com>
> > 
> > This series of patches adds support for first generation of SPI
> > interface
> > for STM32F4 family.
> > 
> First of all, thanks for adding STM32F4 SPI support.

Thanks for your answer and hints for correct approach to this driver.

> > 
> > This version of driver is mostly different to STM32H7 one. Based on
> > linux
> > kernel I2C drivers for STM32 where drivers were splited into
> > STM32F4 and
> > STM32F7 family the same approach seems to be sufficient for SPI
> > STM32
> > drivers. Therefore STM32H7 driver was moved to spi-stm32h7.c file
> > and
> > register and functions were renamed to be more specific to STM32H7.
> > 
> You're right, STM32F4 SPI is slightly different from STM32H7 one: 
> register map/bits offsets are different and STM32H7 has an RX and TX
> FIFO.
> But if you have a look on STM32F7 SPI [1], you'll see that STM32F7
> SPI 
> is based on STM32F4 SPI with new features (data frames & FIFOs) also 
> available on STM32H7 SPI.
> 
> That's why STM32H7 SPI driver was called spi-stm32. The goal was to
> use 
> compatible & match data to differentiate each STM32Fx specificities.
> 
> You can have a look on how it is managed in drivers/rtc/rtc-stm32.c
> (the 
> same driver covers 2 HW version of STM32 RTC), or in 
> drivers/iio/dac/stm32-dac-core.c and stm32-dac.c (the same driver
> also 
> covers 2 HW version of STM32 DAC).
> As your spi-stm32f4.c file is highly based on the existing spi-
> stm32.c 
> file, I think that common code could be factored and specificities
> could 
> be handled with compatible and match data.

I have seen these drivers before. I have been trying to do this for my
previous approach and it is still on my second branch. There was not
too much common parts and I have stuck with complex compatible data
configurations. I thought that was too verbose, therefore I resigned
for it and have gone into idea with two totally different files. I
think I need to get down again to idea you proposed. 

It seems to be more difficult approach and it is gonna take a while
before I send second version of these patches.

Regards,
Cezary

> Regards,
> Amelie
> [1] 
> https://www.st.com/content/ccc/resource/technical/document/reference_
> manual/c5/cf/ef/52/c0/f1/4b/fa/DM00124865.pdf/files/DM00124865.pdf/jc
> r:content/translations/en.DM00124865.pdf
> 
> > 
> > For current version master mode with full-duplex and 8/16 bit data
> > frame
> > format are supported. There is no TX and RX FIFOs like in STM32H7.
> > DMA capabilility is supported for messages longer than arbitrary
> > number
> > of bytes (that is set already to 16 bytes) when TX and RX channels
> > are
> > set at the same time.
> > 
> > Cezary Gapinski (5):
> >    spi: stm32: rename STM32 SPI registers and functions to STM32H7
> >    spi: stm32: rename spi-stm32 to spi-stm32h7
> >    spi: stm32: add driver for STM32F4 controller
> >    ARM: dts: stm32: add SPI support on STM32F429 SoC
> >    spi: stm32: add description about STM32F4 bindings
> > 
> >   .../devicetree/bindings/spi/spi-stm32.txt          |    9 +-
> >   arch/arm/boot/dts/stm32f429.dtsi                   |   60 +
> >   drivers/spi/Kconfig                                |   18 +-
> >   drivers/spi/Makefile                               |    3 +-
> >   drivers/spi/spi-stm32.c                            | 1322 -----
> > --------------
> >   drivers/spi/spi-stm32f4.c                          | 1002
> > +++++++++++++++
> >   drivers/spi/spi-stm32h7.c                          | 1340
> > ++++++++++++++++++++
> >   7 files changed, 2424 insertions(+), 1330 deletions(-)
> >   delete mode 100644 drivers/spi/spi-stm32.c
> >   create mode 100644 drivers/spi/spi-stm32f4.c
> >   create mode 100644 drivers/spi/spi-stm32h7.c

Re: [PATCH 0/5] Add support for STM32F4 SPI

[Amelie DELAUNAY]

Hi Cezary,

On 12/10/18 8:05 PM, Cezary Gapiński wrote:
> Hi Amelie,
> 
> On Mon, 2018-12-10 at 12:37 +0000, Amelie DELAUNAY wrote:
>> Hi Cezary,
>>
>> On 12/9/18 2:53 PM, cezary.gapinski@gmail.com wrote:
>>>
>>> From: Cezary Gapinski <cezary.gapinski@gmail.com>
>>>
>>> This series of patches adds support for first generation of SPI
>>> interface
>>> for STM32F4 family.
>>>
>> First of all, thanks for adding STM32F4 SPI support.
> 
> Thanks for your answer and hints for correct approach to this driver.
> 
>>>
>>> This version of driver is mostly different to STM32H7 one. Based on
>>> linux
>>> kernel I2C drivers for STM32 where drivers were splited into
>>> STM32F4 and
>>> STM32F7 family the same approach seems to be sufficient for SPI
>>> STM32
>>> drivers. Therefore STM32H7 driver was moved to spi-stm32h7.c file
>>> and
>>> register and functions were renamed to be more specific to STM32H7.
>>>
>> You're right, STM32F4 SPI is slightly different from STM32H7 one:
>> register map/bits offsets are different and STM32H7 has an RX and TX
>> FIFO.
>> But if you have a look on STM32F7 SPI [1], you'll see that STM32F7
>> SPI
>> is based on STM32F4 SPI with new features (data frames & FIFOs) also
>> available on STM32H7 SPI.
>>
>> That's why STM32H7 SPI driver was called spi-stm32. The goal was to
>> use
>> compatible & match data to differentiate each STM32Fx specificities.
>>
>> You can have a look on how it is managed in drivers/rtc/rtc-stm32.c
>> (the
>> same driver covers 2 HW version of STM32 RTC), or in
>> drivers/iio/dac/stm32-dac-core.c and stm32-dac.c (the same driver
>> also
>> covers 2 HW version of STM32 DAC).
>> As your spi-stm32f4.c file is highly based on the existing spi-
>> stm32.c
>> file, I think that common code could be factored and specificities
>> could
>> be handled with compatible and match data.
> 
> I have seen these drivers before. I have been trying to do this for my
> previous approach and it is still on my second branch. There was not
> too much common parts and I have stuck with complex compatible data
> configurations. I thought that was too verbose, therefore I resigned
> for it and have gone into idea with two totally different files. I
> think I need to get down again to idea you proposed.
> 
> It seems to be more difficult approach and it is gonna take a while
> before I send second version of these patches.
> 
> Regards,
> Cezary
> 

Sure it isn't the easiest approach but it will be less difficult to add 
STM32F7 SPI support then!

I could test your second version when it will be available, on 
STM32H743i-eval if you don't have one.

Regards,
Amelie

>> Regards,
>> Amelie
>> [1]
>> https://www.st.com/content/ccc/resource/technical/document/reference_
>> manual/c5/cf/ef/52/c0/f1/4b/fa/DM00124865.pdf/files/DM00124865.pdf/jc
>> r:content/translations/en.DM00124865.pdf
>>
>>>
>>> For current version master mode with full-duplex and 8/16 bit data
>>> frame
>>> format are supported. There is no TX and RX FIFOs like in STM32H7.
>>> DMA capabilility is supported for messages longer than arbitrary
>>> number
>>> of bytes (that is set already to 16 bytes) when TX and RX channels
>>> are
>>> set at the same time.
>>>
>>> Cezary Gapinski (5):
>>>     spi: stm32: rename STM32 SPI registers and functions to STM32H7
>>>     spi: stm32: rename spi-stm32 to spi-stm32h7
>>>     spi: stm32: add driver for STM32F4 controller
>>>     ARM: dts: stm32: add SPI support on STM32F429 SoC
>>>     spi: stm32: add description about STM32F4 bindings
>>>
>>>    .../devicetree/bindings/spi/spi-stm32.txt          |    9 +-
>>>    arch/arm/boot/dts/stm32f429.dtsi                   |   60 +
>>>    drivers/spi/Kconfig                                |   18 +-
>>>    drivers/spi/Makefile                               |    3 +-
>>>    drivers/spi/spi-stm32.c                            | 1322 -----
>>> --------------
>>>    drivers/spi/spi-stm32f4.c                          | 1002
>>> +++++++++++++++
>>>    drivers/spi/spi-stm32h7.c                          | 1340
>>> ++++++++++++++++++++
>>>    7 files changed, 2424 insertions(+), 1330 deletions(-)
>>>    delete mode 100644 drivers/spi/spi-stm32.c
>>>    create mode 100644 drivers/spi/spi-stm32f4.c
>>>    create mode 100644 drivers/spi/spi-stm32h7.c
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