From mboxrd@z Thu Jan  1 00:00:00 1970
From: Thierry Reding <thierry.reding@gmail.com>
Subject: Re: [PATCH] spi: tegra20-slink: change chip select action order
Date: Thu, 28 Mar 2019 17:34:16 +0100
Message-ID: <20190328163416.GA31762@ulmo>
References: <20190326143050.26232-1-gaireg@gaireg.de>
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Cc: Laxman Dewangan <ldewangan@nvidia.com>,
        Mark Brown <broonie@kernel.org>,
        Jonathan Hunter <jonathanh@nvidia.com>,
        linux-spi@vger.kernel.org, linux-tegra@vger.kernel.org,
        linux-kernel@vger.kernel.org
To: Randolph =?utf-8?Q?Maa=C3=9Fen?= <gaireg@gaireg.de>
Return-path: <linux-kernel-owner@vger.kernel.org>
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Sender: linux-kernel-owner@vger.kernel.org
List-Id: linux-spi.vger.kernel.org


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On Tue, Mar 26, 2019 at 03:30:50PM +0100, Randolph Maa=C3=9Fen wrote:
> To transfer via SPI the tegra20-slink driver first sets the command
> register, which contains the chip select value, and after that the
> command2 register, which contains the chip select line. This leads to a
> small spike in the chip selct 0 line between the set of the value and
> the selection of the chip select line.
>=20
> This commit changes the order of the register writes so that first the
> chip select line is chosen and then the value is set, removing the
> spike.
>=20
> Signed-off-by: Randolph Maa=C3=9Fen <gaireg@gaireg.de>
> ---
>  drivers/spi/spi-tegra20-slink.c | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)

With the typofix that Sowjanya pointed out, this patch is:

Acked-by: Thierry Reding <treding@nvidia.com>

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