From: Mark Brown <broonie@kernel.org>
To: "Ramuthevar,
Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com>
Cc: robh+dt@kernel.org, mark.rutland@arm.com,
linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, cheol.yong.kim@intel.com,
qi-ming.wu@intel.com
Subject: Re: [PATCH v1 2/2] spi: cadence-qspi: Add QSPI support for Intel LGM SoC
Date: Wed, 18 Sep 2019 13:08:48 +0100 [thread overview]
Message-ID: <20190918120846.GH2596@sirena.co.uk> (raw)
In-Reply-To: <eeefa79b-0a3b-5d62-3a1b-c1e9dcb03aa7@linux.intel.com>
[-- Attachment #1: Type: text/plain, Size: 1051 bytes --]
On Wed, Sep 18, 2019 at 01:59:06PM +0800, Ramuthevar, Vadivel MuruganX wrote:
> On 17/9/2019 11:36 PM, Mark Brown wrote:
> > On Tue, Sep 17, 2019 at 10:11:28AM +0800, Ramuthevar, Vadivel MuruganX wrote:
> > > * spi-cadence.c* in *drivers/spi/*, which supports very old legacy
> > > cadence-spi based devices(normal)
> > > * cadence-quadspi.c(drivers/mtd/spi-nor/)* : specific support to SPI-NOR
> > > flash with new spi-nor layer.
> > > all the API's in this driver purely on spi-nor specific, so couldn't
> > > proceed to adapt.
> > Are these completely separate IPs or are they just different versions of
> > the same IP?
> These are same IPs , but different features Enabled/Disabled depends upon
> the SoC vendors.
> for e.g: Intel LGM SoC uses the same IP, but without DMA and Direct access
> controller.
> also dedicated support to flash devices.
If it's different versions of the same IP then everything should be in
one driver with the optional features enabled depending on what's in a
given system.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
next prev parent reply other threads:[~2019-09-18 12:08 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-16 7:38 [PATCH v1 0/2] spi: cadence-qspi: Add cadence-qspi support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
2019-09-16 7:38 ` [PATCH v1 1/2] dt-bindings: spi: Add support for cadence-qspi IP " Ramuthevar,Vadivel MuruganX
2019-09-30 22:36 ` Rob Herring
2019-10-01 1:13 ` Ramuthevar, Vadivel MuruganX
2019-09-16 7:38 ` [PATCH v1 2/2] spi: cadence-qspi: Add QSPI support for " Ramuthevar,Vadivel MuruganX
2019-09-16 11:32 ` Mark Brown
[not found] ` <466b41c1-3d65-0bf4-6db7-d3b3e06b107b@linux.intel.com>
2019-09-17 15:36 ` Mark Brown
2019-09-18 5:59 ` Ramuthevar, Vadivel MuruganX
2019-09-18 12:08 ` Mark Brown [this message]
2019-09-19 5:45 ` Ramuthevar, Vadivel MuruganX
2019-09-16 13:48 ` kbuild test robot
2019-09-16 16:50 ` [PATCH v1 0/2] spi: cadence-qspi: Add cadence-qspi " Vignesh Raghavendra
2019-09-17 3:31 ` Ramuthevar, Vadivel MuruganX
2019-10-10 1:34 ` Ramuthevar, Vadivel MuruganX
2019-10-10 4:18 ` Vignesh Raghavendra
2019-10-10 5:08 ` Ramuthevar, Vadivel MuruganX
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190918120846.GH2596@sirena.co.uk \
--to=broonie@kernel.org \
--cc=cheol.yong.kim@intel.com \
--cc=devicetree@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=qi-ming.wu@intel.com \
--cc=robh+dt@kernel.org \
--cc=vadivel.muruganx.ramuthevar@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).