From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Shevchenko Subject: Re: [PATCH v2 2/3] spi: Add HiSilicon v3xx SPI NOR flash controller driver Date: Mon, 13 Jan 2020 16:34:03 +0200 Message-ID: <20200113143403.GQ32742@smile.fi.intel.com> References: <20200110140726.GB5889@sirena.org.uk> <6db83881-927c-d11c-9c77-23a45892ddab@huawei.com> <20200110193119.GI32742@smile.fi.intel.com> <612a3c5d-69a4-af6b-5c79-c3fb853193ab@huawei.com> <20200113114256.GH3897@sirena.org.uk> <6dd45da9-9ccf-45f7-ed12-8f1406a0a56b@huawei.com> <20200113140627.GJ3897@sirena.org.uk> <20200113142754.GL3897@sirena.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Cc: John Garry , tudor.ambarus-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org, Linux Kernel Mailing List , chenxiang66-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org, Linuxarm , linux-spi , Marek Vasut , "open list:MEMORY TECHNOLOGY..." , Jiancheng Xue , fengsheng5-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, Mika Westerberg , wanghuiqiang , liusimin4-hv44wF8Li93QT0dZR+AlfA@public.gmane.org To: Mark Brown Return-path: Content-Disposition: inline In-Reply-To: <20200113142754.GL3897-GFdadSzt00ze9xe1eoZjHA@public.gmane.org> Sender: linux-spi-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-ID: On Mon, Jan 13, 2020 at 02:27:54PM +0000, Mark Brown wrote: > On Mon, Jan 13, 2020 at 04:17:32PM +0200, Andy Shevchenko wrote: > > On Mon, Jan 13, 2020 at 4:07 PM Mark Brown wrote: > > > On Mon, Jan 13, 2020 at 01:01:06PM +0000, John Garry wrote: > > > > On 13/01/2020 11:42, Mark Brown wrote: > > > > > > The idiomatic approach appears to be for individual board vendors > > > > > to allocate IDs, you do end up with multiple IDs from multiple > > > > > vendors for the same thing. > > > > > But I am not sure how appropriate that same approach would be for some 3rd > > > > party memory part which we're simply wiring up on our board. Maybe it is. > > > > It seems to be quite common for Intel reference designs to assign > > > Intel IDs to non-Intel parts on the board (which is where I > > > became aware of this practice). > > > Basically vendor of component in question is responsible for ID, but > > it seems they simple don't care. > > AFAICT a lot of the time it seems to be that whoever is writing > the software ends up assigning an ID, that may not be the silicon > vendor. ...which is effectively abusing the ACPI ID allocation procedure. (And yes, Intel itself did it in the past — see badly created ACPI IDs in the drivers) -- With Best Regards, Andy Shevchenko