From: Kamal Dasu <kdasu.kdev@gmail.com>
To: Kamal Dasu <kdasu.kdev@gmail.com>,
bcm-kernel-feedback-list@broadcom.com,
Mark Brown <broonie@kernel.org>
Cc: Justin Chen <justinpopo6@gmail.com>,
linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [Patch v3 5/9] spi: bcm-qspi: when tx/rx buffer is NULL set to 0
Date: Mon, 20 Apr 2020 15:08:49 -0400 [thread overview]
Message-ID: <20200420190853.45614-6-kdasu.kdev@gmail.com> (raw)
In-Reply-To: <20200420190853.45614-1-kdasu.kdev@gmail.com>
From: Justin Chen <justinpopo6@gmail.com>
Currently we set the tx/rx buffer to 0xff when NULL. This causes
problems with some spi slaves where 0xff is a valid command. Looking
at other drivers, the tx/rx buffer is usually set to 0x00 when NULL.
Following this convention solves the issue.
Fixes: fa236a7ef240 ("spi: bcm-qspi: Add Broadcom MSPI driver")
Signed-off-by: Justin Chen <justinpopo6@gmail.com>
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
---
drivers/spi/spi-bcm-qspi.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index c48c399dce53..e00208801c8b 100644
--- a/drivers/spi/spi-bcm-qspi.c
+++ b/drivers/spi/spi-bcm-qspi.c
@@ -669,7 +669,7 @@ static void read_from_hw(struct bcm_qspi *qspi, int slots)
if (buf)
buf[tp.byte] = read_rxram_slot_u8(qspi, slot);
dev_dbg(&qspi->pdev->dev, "RD %02x\n",
- buf ? buf[tp.byte] : 0xff);
+ buf ? buf[tp.byte] : 0x0);
} else {
u16 *buf = tp.trans->rx_buf;
@@ -677,7 +677,7 @@ static void read_from_hw(struct bcm_qspi *qspi, int slots)
buf[tp.byte / 2] = read_rxram_slot_u16(qspi,
slot);
dev_dbg(&qspi->pdev->dev, "RD %04x\n",
- buf ? buf[tp.byte] : 0xffff);
+ buf ? buf[tp.byte / 2] : 0x0);
}
update_qspi_trans_byte_count(qspi, &tp,
@@ -732,13 +732,13 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
while (!tstatus && slot < MSPI_NUM_CDRAM) {
if (tp.trans->bits_per_word <= 8) {
const u8 *buf = tp.trans->tx_buf;
- u8 val = buf ? buf[tp.byte] : 0xff;
+ u8 val = buf ? buf[tp.byte] : 0x00;
write_txram_slot_u8(qspi, slot, val);
dev_dbg(&qspi->pdev->dev, "WR %02x\n", val);
} else {
const u16 *buf = tp.trans->tx_buf;
- u16 val = buf ? buf[tp.byte / 2] : 0xffff;
+ u16 val = buf ? buf[tp.byte / 2] : 0x0000;
write_txram_slot_u16(qspi, slot, val);
dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
--
2.17.1
next prev parent reply other threads:[~2020-04-20 19:10 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20200420190853.45614-1-kdasu.kdev@gmail.com>
2020-04-20 19:08 ` [Patch v3 1/9] spi: bcm-qspi: Handle clock probe deferral Kamal Dasu
2020-04-21 15:06 ` Mark Brown
2020-04-21 17:11 ` Florian Fainelli
2020-04-21 17:15 ` Mark Brown
2020-04-21 17:17 ` Florian Fainelli
2020-04-21 17:20 ` Mark Brown
2020-04-21 18:31 ` Konstantin Ryabitsev
2020-04-21 18:54 ` Mark Brown
2020-04-20 19:08 ` [Patch v3 2/9] dt: bindings: spi: Add support for mspi on brcmstb SoCs Kamal Dasu
2020-04-20 19:08 ` [Patch v3 3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset Kamal Dasu
2020-04-20 19:08 ` [Patch v3 4/9] spi: bcm-qspi: Drive MSPI peripheral SSb pin on cs_change Kamal Dasu
2020-04-20 19:08 ` Kamal Dasu [this message]
2020-04-20 19:08 ` [Patch v3 6/9] spi: bcm-qspi: Make PM suspend/resume work with SCMI clock management Kamal Dasu
2020-04-20 19:08 ` [Patch v3 7/9] spi: bcm-qspi: Use fastbr setting to allow faster MSPI speeds Kamal Dasu
2020-04-20 19:08 ` [Patch v3 8/9] spi: bcm-qspi: add support for MSPI sys clk 108Mhz Kamal Dasu
2020-04-20 19:08 ` [Patch v3 9/9] spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllers Kamal Dasu
2020-04-21 12:50 ` Mark Brown
2020-04-21 14:53 ` Kamal Dasu
2020-04-21 14:59 ` Mark Brown
2020-04-21 18:19 ` Kamal Dasu
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