From: Lars Povlsen <lars.povlsen@microchip.com>
To: Mark Brown <broonie@kernel.org>, Peter Rosin <peda@axentia.se>
Cc: Lars Povlsen <lars.povlsen@microchip.com>,
Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
<linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Serge Semin <fancer.lancer@gmail.com>,
Serge Semin <Sergey.Semin@baikalelectronics.ru>
Subject: [PATCH v3 8/8] arm64: dts: sparx5: Add spi-nand devices
Date: Thu, 2 Jul 2020 12:13:31 +0200 [thread overview]
Message-ID: <20200702101331.26375-9-lars.povlsen@microchip.com> (raw)
In-Reply-To: <20200702101331.26375-1-lars.povlsen@microchip.com>
This patch add spi-nand DT nodes to the applicable Sparx5 boards.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 20 ++++++++++++
.../arm64/boot/dts/microchip/sparx5_nand.dtsi | 32 +++++++++++++++++++
.../boot/dts/microchip/sparx5_pcb125.dts | 7 ++++
.../boot/dts/microchip/sparx5_pcb134.dts | 1 +
.../boot/dts/microchip/sparx5_pcb135.dts | 1 +
5 files changed, 61 insertions(+)
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_nand.dtsi
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 2831935a489e1..21a85359d3492 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -210,6 +210,26 @@ gpio: pinctrl@6110101e0 {
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
+ cs1_pins: cs1-pins {
+ pins = "GPIO_16";
+ function = "si";
+ };
+
+ cs2_pins: cs2-pins {
+ pins = "GPIO_17";
+ function = "si";
+ };
+
+ cs3_pins: cs3-pins {
+ pins = "GPIO_18";
+ function = "si";
+ };
+
+ si2_pins: si2-pins {
+ pins = "GPIO_39", "GPIO_40", "GPIO_41";
+ function = "si2";
+ };
+
uart_pins: uart-pins {
pins = "GPIO_10", "GPIO_11";
function = "uart";
diff --git a/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi
new file mode 100644
index 0000000000000..fd9523d9efbe3
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+&gpio {
+ cs14_pins: cs14-pins {
+ pins = "GPIO_44";
+ function = "si";
+ };
+};
+
+&mux {
+ /* CS14 (NAND) is on SPI2 */
+ mux@e {
+ reg = <14>;
+ microchip,bus-interface = <1>;
+ };
+};
+
+&spi0 {
+ pinctrl-0 = <&si2_pins>;
+ pinctrl-names = "default";
+ spi-flash@e {
+ compatible = "spi-nand";
+ pinctrl-0 = <&cs14_pins>;
+ pinctrl-names = "default";
+ spi-max-frequency = <42000000>;
+ reg = <14>;
+ snps,rx-sample-delay-ns = <7>; /* Tune for speed */
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
index d8b5d23abfab0..94c4c3fd5a786 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
@@ -46,6 +46,13 @@ spi-flash@0 {
spi-max-frequency = <8000000>; /* input clock */
reg = <0>; /* CS0 */
};
+ spi-flash@1 {
+ compatible = "spi-nand";
+ pinctrl-0 = <&cs1_pins>;
+ pinctrl-names = "default";
+ spi-max-frequency = <8000000>;
+ reg = <1>; /* CS1 */
+ };
};
&i2c1 {
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
index feee4e99ff57c..45ca1af7e8500 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include "sparx5_pcb134_board.dtsi"
+#include "sparx5_nand.dtsi"
/ {
model = "Sparx5 PCB134 Reference Board (NAND)";
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
index 20e409a9be196..647cdb38b1130 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include "sparx5_pcb135_board.dtsi"
+#include "sparx5_nand.dtsi"
/ {
model = "Sparx5 PCB135 Reference Board (NAND)";
--
2.27.0
prev parent reply other threads:[~2020-07-02 10:15 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-02 10:13 [PATCH v3 0/8] spi: Adding support for Microchip Sparx5 SoC Lars Povlsen
2020-07-02 10:13 ` [PATCH v3 1/8] spi: dw: Add support for RX sample delay register Lars Povlsen
2020-07-02 10:13 ` [PATCH v3 2/8] arm64: dts: sparx5: Add SPI controller and SPI mux Lars Povlsen
2020-07-02 10:13 ` [PATCH v3 3/8] spi: dw: Add Microchip Sparx5 support Lars Povlsen
2020-07-02 10:13 ` [PATCH v3 4/8] mux: sparx5: Add Sparx5 SPI mux driver Lars Povlsen
2020-07-02 11:33 ` Lars Povlsen
2020-07-02 11:36 ` Peter Rosin
2020-07-03 9:14 ` Lars Povlsen
2020-07-02 10:13 ` [PATCH v3 5/8] dt-bindings: snps,dw-apb-ssi: Add sparx5 support, plus snps,rx-sample-delay-ns property Lars Povlsen
2020-07-13 19:22 ` Rob Herring
2020-07-13 19:52 ` Serge Semin
2020-07-14 8:30 ` Lars Povlsen
2020-07-02 10:13 ` [PATCH v3 6/8] dt-bindings: microchip,sparx5-spi-mux: Add Sparx5 SPI mux driver bindings Lars Povlsen
2020-07-13 19:29 ` Rob Herring
2020-07-14 8:52 ` Lars Povlsen
2020-07-02 10:13 ` [PATCH v3 7/8] arm64: dts: sparx5: Add spi-nor support Lars Povlsen
2020-07-02 10:13 ` Lars Povlsen [this message]
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