From: Lars Povlsen <lars.povlsen@microchip.com>
To: Mark Brown <broonie@kernel.org>, Peter Rosin <peda@axentia.se>
Cc: Lars Povlsen <lars.povlsen@microchip.com>,
Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
<linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Serge Semin <fancer.lancer@gmail.com>,
Serge Semin <Sergey.Semin@baikalelectronics.ru>
Subject: [PATCH v5 6/6] arm64: dts: sparx5: Add spi-nand devices
Date: Mon, 24 Aug 2020 22:30:10 +0200 [thread overview]
Message-ID: <20200824203010.2033-7-lars.povlsen@microchip.com> (raw)
In-Reply-To: <20200824203010.2033-1-lars.povlsen@microchip.com>
This patch add spi-nand DT nodes to the applicable Sparx5 boards.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 20 ++++++++++++
.../arm64/boot/dts/microchip/sparx5_nand.dtsi | 31 +++++++++++++++++++
.../boot/dts/microchip/sparx5_pcb125.dts | 14 +++++++++
.../boot/dts/microchip/sparx5_pcb134.dts | 1 +
.../boot/dts/microchip/sparx5_pcb135.dts | 1 +
5 files changed, 67 insertions(+)
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_nand.dtsi
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 89ac1a710216..f7ddfad3c318 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -212,6 +212,26 @@ gpio: pinctrl@6110101e0 {
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
+ cs1_pins: cs1-pins {
+ pins = "GPIO_16";
+ function = "si";
+ };
+
+ cs2_pins: cs2-pins {
+ pins = "GPIO_17";
+ function = "si";
+ };
+
+ cs3_pins: cs3-pins {
+ pins = "GPIO_18";
+ function = "si";
+ };
+
+ si2_pins: si2-pins {
+ pins = "GPIO_39", "GPIO_40", "GPIO_41";
+ function = "si2";
+ };
+
uart_pins: uart-pins {
pins = "GPIO_10", "GPIO_11";
function = "uart";
diff --git a/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi
new file mode 100644
index 000000000000..03f107e427d7
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+&gpio {
+ cs14_pins: cs14-pins {
+ pins = "GPIO_44";
+ function = "si";
+ };
+};
+
+&spi0 {
+ pinctrl-0 = <&si2_pins>;
+ pinctrl-names = "default";
+ spi@e {
+ compatible = "spi-mux";
+ mux-controls = <&mux>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <14>; /* CS14 */
+ spi-flash@6 {
+ compatible = "spi-nand";
+ pinctrl-0 = <&cs14_pins>;
+ pinctrl-names = "default";
+ reg = <0x6>; /* SPI2 */
+ spi-max-frequency = <42000000>;
+ rx-sample-delay-ns = <7>; /* Tune for speed */
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
index c1eb1d661174..6b2da7c7520c 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
@@ -53,6 +53,20 @@ spi-flash@9 {
reg = <0x9>; /* SPI */
};
};
+ spi@1 {
+ compatible = "spi-mux";
+ mux-controls = <&mux 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>; /* CS1 */
+ spi-flash@9 {
+ compatible = "spi-nand";
+ pinctrl-0 = <&cs1_pins>;
+ pinctrl-names = "default";
+ spi-max-frequency = <8000000>;
+ reg = <0x9>; /* SPI */
+ };
+ };
};
&i2c1 {
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
index feee4e99ff57..45ca1af7e850 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include "sparx5_pcb134_board.dtsi"
+#include "sparx5_nand.dtsi"
/ {
model = "Sparx5 PCB134 Reference Board (NAND)";
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
index 20e409a9be19..647cdb38b113 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include "sparx5_pcb135_board.dtsi"
+#include "sparx5_nand.dtsi"
/ {
model = "Sparx5 PCB135 Reference Board (NAND)";
--
2.27.0
next prev parent reply other threads:[~2020-08-24 20:31 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-24 20:30 [PATCH v5 0/6] spi: Adding support for Microchip Sparx5 SoC Lars Povlsen
2020-08-24 20:30 ` [PATCH v5 1/6] spi: dw: Add support for RX sample delay register Lars Povlsen
2020-08-24 20:30 ` [PATCH v5 2/6] spi: dw: Add Microchip Sparx5 support Lars Povlsen
2020-08-24 20:30 ` [PATCH v5 3/6] arm64: dts: sparx5: Add SPI controller and associated mmio-mux Lars Povlsen
2020-08-24 20:30 ` [PATCH v5 4/6] dt-bindings: snps,dw-apb-ssi: Add sparx5 support, plus rx-sample-delay-ns property Lars Povlsen
2020-08-28 21:57 ` [PATCH v5 4/6] dt-bindings: snps, dw-apb-ssi: " Rob Herring
2020-08-24 20:30 ` [PATCH v5 5/6] arm64: dts: sparx5: Add spi-nor support Lars Povlsen
2020-08-24 20:30 ` Lars Povlsen [this message]
2020-09-08 17:20 ` [PATCH v5 0/6] spi: Adding support for Microchip Sparx5 SoC Mark Brown
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