From: Rob Herring <robh@kernel.org>
To: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Cc: broonie@kernel.org, joel@jms.id.au, andrew@aj.id.au,
clg@kaod.org, bbrezillon@kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-aspeed@lists.ozlabs.org,
linux-spi@vger.kernel.org, BMC-SW@aspeedtech.com
Subject: Re: [v2 1/4] dt-bindings: spi: Add binding file for ASPEED FMC/SPI memory controller
Date: Thu, 5 Nov 2020 12:40:36 -0600 [thread overview]
Message-ID: <20201105184036.GA1607865@bogus> (raw)
In-Reply-To: <20201103072202.24705-2-chin-ting_kuo@aspeedtech.com>
On Tue, Nov 03, 2020 at 03:21:59PM +0800, Chin-Ting Kuo wrote:
> Create binding file with YAML syntax for ASPEED FMC/SPI memory controller.
>
> Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> ---
> .../bindings/spi/aspeed,spi-aspeed.yaml | 66 +++++++++++++++++++
> 1 file changed, 66 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/aspeed,spi-aspeed.yaml
>
> diff --git a/Documentation/devicetree/bindings/spi/aspeed,spi-aspeed.yaml b/Documentation/devicetree/bindings/spi/aspeed,spi-aspeed.yaml
> new file mode 100644
> index 000000000000..41b9692c7226
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/aspeed,spi-aspeed.yaml
> @@ -0,0 +1,66 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/aspeed,spi-aspeed.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SPI memory controller for ASPEED SoCs
> +
> +maintainers:
> + - Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> +
> +description: |
> + There are three SPI memory controllers embedded in a ASPEED SoC.
> + They are usually connected to SPI NOR flashes. Each of them has
> + more than a chip select. They also support SPI single, dual and
> + quad IO modes for SPI NOR flash.
> +
> +allOf:
> + - $ref: /spi/spi-controller.yaml#
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - aspeed,ast2600-fmc
> + - aspeed,ast2600-spi
> +
> + reg:
> + items:
> + - description: the control register location and length
> + - description: the flash memory mapping address and length
> +
> + clocks:
> + description: AHB bus clock which will be converted to SPI bus clock
Need to define how many clocks (maxItems: 1).
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - num-cs
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/ast2600-clock.h>
> + spi1: spi@1e630000 {
> + compatible = "aspeed,ast2600-spi";
> + reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>;
> + reg-names = "spi_ctrl_reg", "spi_mmap";
> + clocks = <&syscon ASPEED_CLK_AHB>;
> + num-cs = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <50000000>;
> + };
> + flash@1 {
> + compatible = "jedec,spi-nor";
> + reg = <1>;
> + spi-max-frequency = <50000000>;
> + };
> + };
> --
> 2.17.1
>
next prev parent reply other threads:[~2020-11-05 18:40 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-03 7:21 [v2 0/4] Porting ASPEED FMC/SPI memory controller driver Chin-Ting Kuo
2020-11-03 7:21 ` [v2 1/4] dt-bindings: spi: Add binding file for ASPEED FMC/SPI memory controller Chin-Ting Kuo
2020-11-05 18:40 ` Rob Herring [this message]
2020-11-06 9:03 ` Chin-Ting Kuo
2020-11-03 7:22 ` [v2 2/4] ARM: dts: aspeed: ast2600: Update FMC/SPI controller setting for spi-aspeed.c Chin-Ting Kuo
2020-11-03 7:22 ` [v2 3/4] ARM: dts: aspeed: ast2600-evb: Adjust SPI flash configuration Chin-Ting Kuo
2020-11-03 7:22 ` [v2 4/4] spi: aspeed: Add ASPEED FMC/SPI memory controller driver Chin-Ting Kuo
2020-11-04 20:39 ` Mark Brown
2020-11-05 11:27 ` Chin-Ting Kuo
2020-12-01 13:57 ` [v2 0/4] Porting " Mark Brown
2020-12-02 21:19 ` Joel Stanley
2020-12-03 10:32 ` Mark Brown
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