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Date:   Wed, 22 Dec 2021 09:12:23 +0100
From:   Miquel Raynal <miquel.raynal@bootlin.com>
To:     Pratyush Yadav <p.yadav@ti.com>
Cc:     Richard Weinberger <richard@nod.at>,
        Vignesh Raghavendra <vigneshr@ti.com>,
        Tudor Ambarus <Tudor.Ambarus@microchip.com>,
        Michael Walle <michael@walle.cc>,
        <linux-mtd@lists.infradead.org>, Mark Brown <broonie@kernel.org>,
        <linux-spi@vger.kernel.org>, Julien Su <juliensu@mxic.com.tw>,
        Jaime Liao <jaimeliao@mxic.com.tw>,
        Boris Brezillon <boris.brezillon@collabora.com>,
        Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
        Xiangsheng Hou <xiangsheng.hou@mediatek.com>
Subject: Re: [PATCH v8 01/14] spi: spi-mem: reject partial cycle transfers
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Message-ID: <20211222091223.5bf11221@xps13>
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        <20211221184148.pw4blwxdvxcoerjo@ti.com>
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Hi Pratyush,

p.yadav@ti.com wrote on Wed, 22 Dec 2021 00:11:50 +0530:

> Hi,
> 
> On 21/12/21 06:48PM, Miquel Raynal wrote:
> > From: Pratyush Yadav <p.yadav@ti.com>
> > 
> > In 8D-8D-8D mode two bytes are transferred per cycle. So an odd number
> > of bytes cannot be transferred because it would leave a residual half
> > cycle at the end. Consider such a transfer invalid and reject it.
> > 
> > Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> > Reviewed-by: Mark Brown <broonie@kernel.org>
> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>  
> 
> Sorry, I didn't realize this before. This patch would break a couple of 
> SPI NOR flashes. You need patch 1, 2, and 3 from my series as well to 
> make sure this does not happen. Since those patches have some pending 
> comments, can you just drop this patch and I will re-roll it on top of 
> your series later when I can find some time for it? Again, sorry for not 
> noticing this before.

Yes no problem, I might as well drop it when applying.

Thanks,
Miquèl