* [PATCH V4 1/3] dt-bindings: spi: Convert spi-slave-mt27xx to json-schema
2022-01-25 1:23 [PATCH V4 0/3] Add compatible for Mediatek MT8186 Leilk Liu
@ 2022-01-25 1:23 ` Leilk Liu
2022-02-04 23:03 ` Rob Herring
2022-01-25 1:23 ` [PATCH V4 2/3] dt-bindings: spi: Convert spi-mt65xx " Leilk Liu
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Leilk Liu @ 2022-01-25 1:23 UTC (permalink / raw)
To: Mark Brown, Rob Herring
Cc: Matthias Brugger, devicetree, linux-kernel, linux-arm-kernel,
linux-spi, linux-mediatek, Leilk Liu
Convert Mediatek ARM SOC's SPI Slave controller binding
to json-schema format.
Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
---
.../spi/mediatek,spi-slave-mt27xx.yaml | 58 +++++++++++++++++++
.../bindings/spi/spi-slave-mt27xx.txt | 33 -----------
2 files changed, 58 insertions(+), 33 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/mediatek,spi-slave-mt27xx.yaml
delete mode 100644 Documentation/devicetree/bindings/spi/spi-slave-mt27xx.txt
diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-slave-mt27xx.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-slave-mt27xx.yaml
new file mode 100644
index 000000000000..7977799a8ee1
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/mediatek,spi-slave-mt27xx.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/mediatek,spi-slave-mt27xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SPI Slave controller for MediaTek ARM SoCs
+
+maintainers:
+ - Leilk Liu <leilk.liu@mediatek.com>
+
+allOf:
+ - $ref: "/schemas/spi/spi-controller.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt2712-spi-slave
+ - mediatek,mt8195-spi-slave
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: spi
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt2712-clk.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ spi@10013000 {
+ compatible = "mediatek,mt2712-spi-slave";
+ reg = <0x10013000 0x100>;
+ interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_AO_SPI1>;
+ clock-names = "spi";
+ assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
+ };
diff --git a/Documentation/devicetree/bindings/spi/spi-slave-mt27xx.txt b/Documentation/devicetree/bindings/spi/spi-slave-mt27xx.txt
deleted file mode 100644
index 9192724540fd..000000000000
--- a/Documentation/devicetree/bindings/spi/spi-slave-mt27xx.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-Binding for MTK SPI Slave controller
-
-Required properties:
-- compatible: should be one of the following.
- - mediatek,mt2712-spi-slave: for mt2712 platforms
- - mediatek,mt8195-spi-slave: for mt8195 platforms
-- reg: Address and length of the register set for the device.
-- interrupts: Should contain spi interrupt.
-- clocks: phandles to input clocks.
- It's clock gate, and should be <&infracfg CLK_INFRA_AO_SPI1>.
-- clock-names: should be "spi" for the clock gate.
-
-Optional properties:
-- assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>.
-- assigned-clock-parents: parent of mux clock.
- It's PLL, and should be one of the following.
- - <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ.
- It's the default one.
- - <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ.
- - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
- - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
-
-Example:
-- SoC Specific Portion:
-spis1: spi@10013000 {
- compatible = "mediatek,mt2712-spi-slave";
- reg = <0 0x10013000 0 0x100>;
- interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&infracfg CLK_INFRA_AO_SPI1>;
- clock-names = "spi";
- assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
-};
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH V4 2/3] dt-bindings: spi: Convert spi-mt65xx to json-schema
2022-01-25 1:23 [PATCH V4 0/3] Add compatible for Mediatek MT8186 Leilk Liu
2022-01-25 1:23 ` [PATCH V4 1/3] dt-bindings: spi: Convert spi-slave-mt27xx to json-schema Leilk Liu
@ 2022-01-25 1:23 ` Leilk Liu
2022-02-04 23:15 ` Rob Herring
2022-01-25 1:23 ` [PATCH V4 3/3] dt-bindings: spi: Add compatible for Mediatek MT8186 Leilk Liu
2022-02-08 19:00 ` [PATCH V4 0/3] " Mark Brown
3 siblings, 1 reply; 7+ messages in thread
From: Leilk Liu @ 2022-01-25 1:23 UTC (permalink / raw)
To: Mark Brown, Rob Herring
Cc: Matthias Brugger, devicetree, linux-kernel, linux-arm-kernel,
linux-spi, linux-mediatek, Leilk Liu
Convert Mediatek ARM SOC's SPI Master controller binding
to json-schema format.
Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
---
.../bindings/spi/mediatek,spi-mt65xx.yaml | 101 ++++++++++++++++++
.../devicetree/bindings/spi/spi-mt65xx.txt | 68 ------------
2 files changed, 101 insertions(+), 68 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
delete mode 100644 Documentation/devicetree/bindings/spi/spi-mt65xx.txt
diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
new file mode 100644
index 000000000000..ea977fba49a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SPI Bus controller for MediaTek ARM SoCs
+
+maintainers:
+ - Leilk Liu <leilk.liu@mediatek.com>
+
+allOf:
+ - $ref: "/schemas/spi/spi-controller.yaml#"
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - mediatek,mt7629-spi
+ - const: mediatek,mt7622-spi
+ - items:
+ - enum:
+ - mediatek,mt8516-spi
+ - const: mediatek,mt2712-spi
+ - items:
+ - enum:
+ - mediatek,mt6779-spi
+ - mediatek,mt8192-spi
+ - mediatek,mt8195-spi
+ - const: mediatek,mt6765-spi
+ - items:
+ - enum:
+ - mediatek,mt2701-spi
+ - mediatek,mt2712-spi
+ - mediatek,mt6589-spi
+ - mediatek,mt6765-spi
+ - mediatek,mt6893-spi
+ - mediatek,mt7622-spi
+ - mediatek,mt8135-spi
+ - mediatek,mt8173-spi
+ - mediatek,mt8183-spi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: clock used for the parent clock
+ - description: clock used for the muxes clock
+ - description: clock used for the clock gate
+
+ clock-names:
+ items:
+ - const: parent-clk
+ - const: sel-clk
+ - const: spi-clk
+
+ mediatek,pad-select:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ maxItems: 4
+ items:
+ enum: [0, 1, 2, 3]
+ description:
+ specify which pins group(ck/mi/mo/cs) spi controller used.
+ This is an array.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - '#address-cells'
+ - '#size-cells'
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ spi@1100a000 {
+ compatible = "mediatek,mt8173-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1100a000 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&pericfg CLK_PERI_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;
+ mediatek,pad-select = <1>, <0>;
+ };
diff --git a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
deleted file mode 100644
index 2a24969159cc..000000000000
--- a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
+++ /dev/null
@@ -1,68 +0,0 @@
-Binding for MTK SPI controller
-
-Required properties:
-- compatible: should be one of the following.
- - mediatek,mt2701-spi: for mt2701 platforms
- - mediatek,mt2712-spi: for mt2712 platforms
- - mediatek,mt6589-spi: for mt6589 platforms
- - mediatek,mt6765-spi: for mt6765 platforms
- - mediatek,mt7622-spi: for mt7622 platforms
- - "mediatek,mt7629-spi", "mediatek,mt7622-spi": for mt7629 platforms
- - mediatek,mt8135-spi: for mt8135 platforms
- - mediatek,mt8173-spi: for mt8173 platforms
- - mediatek,mt8183-spi: for mt8183 platforms
- - mediatek,mt6893-spi: for mt6893 platforms
- - "mediatek,mt8192-spi", "mediatek,mt6765-spi": for mt8192 platforms
- - "mediatek,mt8195-spi", "mediatek,mt6765-spi": for mt8195 platforms
- - "mediatek,mt8516-spi", "mediatek,mt2712-spi": for mt8516 platforms
- - "mediatek,mt6779-spi", "mediatek,mt6765-spi": for mt6779 platforms
-
-- #address-cells: should be 1.
-
-- #size-cells: should be 0.
-
-- reg: Address and length of the register set for the device
-
-- interrupts: Should contain spi interrupt
-
-- clocks: phandles to input clocks.
- The first should be one of the following. It's PLL.
- - <&clk26m>: specify parent clock 26MHZ.
- - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
- It's the default one.
- - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
- - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
- - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
- The second should be <&topckgen CLK_TOP_SPI_SEL>. It's clock mux.
- The third is <&pericfg CLK_PERI_SPI0>. It's clock gate.
-
-- clock-names: shall be "parent-clk" for the parent clock, "sel-clk" for the
- muxes clock, and "spi-clk" for the clock gate.
-
-Optional properties:
--cs-gpios: see spi-bus.txt.
-
-- mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi
- controller used. This is an array, the element value should be 0~3,
- only required for MT8173.
- 0: specify GPIO69,70,71,72 for spi pins.
- 1: specify GPIO102,103,104,105 for spi pins.
- 2: specify GPIO128,129,130,131 for spi pins.
- 3: specify GPIO5,6,7,8 for spi pins.
-
-Example:
-
-- SoC Specific Portion:
-spi: spi@1100a000 {
- compatible = "mediatek,mt8173-spi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0 0x1100a000 0 0x1000>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
- <&topckgen CLK_TOP_SPI_SEL>,
- <&pericfg CLK_PERI_SPI0>;
- clock-names = "parent-clk", "sel-clk", "spi-clk";
- cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;
- mediatek,pad-select = <1>, <0>;
-};
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread