From: Tudor Ambarus <tudor.ambarus@microchip.com>
To: <p.yadav@ti.com>, <michael@walle.cc>, <broonie@kernel.org>
Cc: <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>,
<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<linux-spi@vger.kernel.org>, <nicolas.ferre@microchip.com>,
Tudor Ambarus <tudor.ambarus@microchip.com>
Subject: [PATCH v2 5/6] mtd: spi-nor: core: Introduce SPI_NOR_SOFT_RESET flash_info fixup_flag
Date: Fri, 11 Mar 2022 10:01:46 +0200 [thread overview]
Message-ID: <20220311080147.453483-6-tudor.ambarus@microchip.com> (raw)
In-Reply-To: <20220311080147.453483-1-tudor.ambarus@microchip.com>
The Soft Reset and Rescue Sequence Support is defined in BFPT_DWORD(16)
starting with JESD216A. The first version of SFDP, JESD216 (April 2011),
defines just the first 9 BFPT DWORDS, thus it does not contain information
about the Software Reset and Rescue Support. Since this support can not
be discovered by parsing the first SFDP version, introduce a flash_info
fixup_flag that will be used either by flashes that define
JESD216 (April 2011) or by flashes that do not define SFDP at all.
In case a flash defines BFPT_DWORD(16) but with wrong values, one should
instead use a post_bfpt() hook and set SNOR_F_SOFT_RESET.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20220209133656.374903-7-tudor.ambarus@microchip.com
---
drivers/mtd/spi-nor/core.c | 3 +++
drivers/mtd/spi-nor/core.h | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index d7eebbd01122..7da8cf559dfd 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2417,6 +2417,9 @@ static void spi_nor_init_fixup_flags(struct spi_nor *nor)
if (fixup_flags & SPI_NOR_IO_MODE_EN_VOLATILE)
nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE;
+
+ if (fixup_flags & SPI_NOR_SOFT_RESET)
+ nor->flags |= SNOR_F_SOFT_RESET;
}
/**
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 4508bbea5df1..fa716e467330 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -483,6 +483,8 @@ struct spi_nor_fixups {
* memory size above 128Mib.
* SPI_NOR_IO_MODE_EN_VOLATILE: flash enables the best available I/O mode
* via a volatile bit.
+ * SPI_NOR_SOFT_RESET: flash supports software reset enable, reset
+ * sequence.
* @mfr_flags: manufacturer private flags. Used in the manufacturer fixup
* hooks to differentiate support between flashes of the same
* manufacturer.
@@ -524,6 +526,7 @@ struct flash_info {
u8 fixup_flags;
#define SPI_NOR_4B_OPCODES BIT(0)
#define SPI_NOR_IO_MODE_EN_VOLATILE BIT(1)
+#define SPI_NOR_SOFT_RESET BIT(2)
u8 mfr_flags;
--
2.25.1
next prev parent reply other threads:[~2022-03-11 8:02 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-11 8:01 [PATCH v2 0/6] spi-mem: Allow specifying the byte order in DTR mode Tudor Ambarus
2022-03-11 8:01 ` [PATCH v2 1/6] spi: " Tudor Ambarus
2022-03-11 8:01 ` [PATCH v2 2/6] mtd: spi-nor: core: " Tudor Ambarus
2022-03-11 8:01 ` [PATCH v2 3/6] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT Tudor Ambarus
2022-03-11 8:01 ` [PATCH v2 4/6] mtd: spi-nor: core: Introduce SPI_NOR_DTR_BSWAP16 no_sfdp_flag Tudor Ambarus
2022-03-11 8:01 ` Tudor Ambarus [this message]
2022-03-11 8:01 ` [PATCH v2 6/6] mtd: spi-nor: macronix: Add support for mx66lm1g45g Tudor Ambarus
2022-03-15 6:08 ` [PATCH v2 0/6] spi-mem: Allow specifying the byte order in DTR mode Vignesh Raghavendra
2022-03-15 6:58 ` Tudor.Ambarus
2022-03-16 7:08 ` Vignesh Raghavendra
2022-03-16 8:39 ` Michael Walle
2022-03-15 7:19 ` Michael Walle
2022-03-16 7:05 ` Vignesh Raghavendra
2022-03-16 7:57 ` Tudor.Ambarus
2022-03-16 13:55 ` David Laight
2022-03-17 9:40 ` Michael Walle
2022-03-17 10:14 ` David Laight
2022-03-17 10:23 ` Vignesh Raghavendra
2022-03-17 11:10 ` David Laight
2022-03-17 16:49 ` Vignesh Raghavendra
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