From: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
To: <broonie@kernel.org>, <robh+dt@kernel.org>, <krzk+dt@kernel.org>
Cc: <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<claudiu.beznea@microchip.com>, <tudor.ambarus@microchip.com>,
<linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <UNGLinuxDriver@microchip.com>,
<Kavyasree.Kotagiri@microchip.com>, <Manohar.Puri@microchip.com>
Subject: [PATCH] spi: atmel,quadspi: Define lan966x QSPI
Date: Thu, 7 Apr 2022 16:24:20 +0530 [thread overview]
Message-ID: <20220407105420.10765-1-kavyasree.kotagiri@microchip.com> (raw)
LAN966x SoC supports 3 QSPI controllers. Each of them support
data and clock frequency upto 100Mhz DDR and QUAD protocol.
Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
---
Documentation/devicetree/bindings/spi/atmel,quadspi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml
index 1d493add4053..100d6e7f2748 100644
--- a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml
+++ b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml
@@ -19,6 +19,7 @@ properties:
- microchip,sam9x60-qspi
- microchip,sama7g5-qspi
- microchip,sama7g5-ospi
+ - microchip,lan966x-qspi
reg:
items:
--
2.17.1
next reply other threads:[~2022-04-07 10:54 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-07 10:54 Kavyasree Kotagiri [this message]
2022-04-07 11:02 ` [PATCH] spi: atmel,quadspi: Define lan966x QSPI Mark Brown
2022-04-07 11:23 ` Michael Walle
2022-04-07 11:31 ` Mark Brown
2022-04-07 11:41 ` Michael Walle
2022-04-07 12:04 ` Krzysztof Kozlowski
2022-04-07 12:05 ` Krzysztof Kozlowski
2022-04-07 12:54 ` Tudor.Ambarus
2022-04-08 11:52 ` Kavyasree.Kotagiri
2022-04-11 14:46 ` Michael Walle
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