From: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
To: <broonie@kernel.org>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>
Cc: <akumarma@amd.com>, <git@amd.com>, <michal.simek@xilinx.com>,
<linux-spi@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<amit.kumar-mahapatra@amd.com>,
Rajan Vaja <rajan.vaja@xilinx.com>,
Michal Simek <michal.simek@amd.com>,
Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Subject: [RESEND PATCH v3 4/7] firmware: xilinx: Add qspi firmware interface
Date: Mon, 26 Sep 2022 12:03:24 +0530 [thread overview]
Message-ID: <20220926063327.20753-5-amit.kumar-mahapatra@xilinx.com> (raw)
In-Reply-To: <20220926063327.20753-1-amit.kumar-mahapatra@xilinx.com>
From: Rajan Vaja <rajan.vaja@xilinx.com>
Add support for QSPI ioctl functions and enums.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
---
drivers/firmware/xilinx/zynqmp.c | 7 +++++++
include/linux/firmware/xlnx-zynqmp.h | 19 +++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index d1f652802181..5d709faf9fe2 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -843,6 +843,13 @@ int zynqmp_pm_read_pggs(u32 index, u32 *value)
}
EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs);
+int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)
+{
+ return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_SET_TAPDELAY_BYPASS,
+ index, value, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_set_tapdelay_bypass);
+
/**
* zynqmp_pm_set_boot_health_status() - PM API for setting healthy boot status
* @value: Status value to be written
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 9f50dacbf7d6..0a84b04af26e 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -135,6 +135,7 @@ enum pm_ret_status {
};
enum pm_ioctl_id {
+ IOCTL_SET_TAPDELAY_BYPASS = 4,
IOCTL_SD_DLL_RESET = 6,
IOCTL_SET_SD_TAPDELAY = 7,
IOCTL_SET_PLL_FRAC_MODE = 8,
@@ -386,6 +387,18 @@ enum zynqmp_pm_shutdown_subtype {
ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
};
+enum tap_delay_signal_type {
+ PM_TAPDELAY_NAND_DQS_IN = 0,
+ PM_TAPDELAY_NAND_DQS_OUT = 1,
+ PM_TAPDELAY_QSPI = 2,
+ PM_TAPDELAY_MAX = 3,
+};
+
+enum tap_delay_bypass_ctrl {
+ PM_TAPDELAY_BYPASS_DISABLE = 0,
+ PM_TAPDELAY_BYPASS_ENABLE = 1,
+};
+
enum ospi_mux_select_type {
PM_OSPI_MUX_SEL_DMA = 0,
PM_OSPI_MUX_SEL_LINEAR = 1,
@@ -457,6 +470,7 @@ int zynqmp_pm_write_ggs(u32 index, u32 value);
int zynqmp_pm_read_ggs(u32 index, u32 *value);
int zynqmp_pm_write_pggs(u32 index, u32 value);
int zynqmp_pm_read_pggs(u32 index, u32 *value);
+int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value);
int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
int zynqmp_pm_set_boot_health_status(u32 value);
int zynqmp_pm_pinctrl_request(const u32 pin);
@@ -666,6 +680,11 @@ static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
return -ENODEV;
}
+static inline int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)
+{
+ return -ENODEV;
+}
+
static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
{
return -ENODEV;
--
2.17.1
next prev parent reply other threads:[~2022-09-26 6:34 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-26 6:33 [RESEND PATCH v3 0/7] spi: spi-zyqnmp-gqspi: Add tap delay and Versal platform support Amit Kumar Mahapatra
2022-09-26 6:33 ` [RESEND PATCH v3 1/7] spi: spi-zynqmp-gqspi: Fix kernel-doc warnings Amit Kumar Mahapatra
2022-09-26 6:33 ` [RESEND PATCH v3 2/7] spi: spi-zynqmp-gqspi: Set CPOL and CPHA during hardware init Amit Kumar Mahapatra
2022-09-26 6:33 ` [RESEND PATCH v3 3/7] spi: spi-zynqmp-gqspi: Avoid setting baud rate multiple times for same SPI frequency Amit Kumar Mahapatra
2022-09-26 6:33 ` Amit Kumar Mahapatra [this message]
2022-09-26 6:33 ` [RESEND PATCH v3 5/7] spi: spi-zynqmp-gqspi: Add tap delay support for ZynqMP GQSPI Controller Amit Kumar Mahapatra
2022-09-26 6:33 ` [RESEND PATCH v3 6/7] dt-bindings: spi: spi-zynqmp-qspi: Add support for Xilinx Versal QSPI Amit Kumar Mahapatra
2022-09-26 9:01 ` Krzysztof Kozlowski
2022-09-27 9:40 ` Mahapatra, Amit Kumar
2022-09-26 6:33 ` [RESEND PATCH v3 7/7] spi: spi-zynqmp-gqspi: Add tap delay support for GQSPI controller on Versal platform Amit Kumar Mahapatra
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220926063327.20753-5-amit.kumar-mahapatra@xilinx.com \
--to=amit.kumar-mahapatra@xilinx.com \
--cc=akumarma@amd.com \
--cc=amit.kumar-mahapatra@amd.com \
--cc=broonie@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=git@amd.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
--cc=michal.simek@amd.com \
--cc=michal.simek@xilinx.com \
--cc=rajan.vaja@xilinx.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).