From: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
To: <linux-spi@vger.kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <broonie@kernel.org>
Subject: [PATCH SPI for-next 3/3] spi: mchp-pci1xxxx: Fix improper implementation of disabling chip select lines
Date: Tue, 4 Apr 2023 22:46:13 +0530 [thread overview]
Message-ID: <20230404171613.1336093-4-tharunkumar.pasumarthi@microchip.com> (raw)
In-Reply-To: <20230404171613.1336093-1-tharunkumar.pasumarthi@microchip.com>
Hardware does not have support to disable individual chip select lines.
Disable all chip select lines by using SPI_FORCE_CE bit.
Fixes: 1cc0cbea7167 ("spi: microchip: pci1xxxx: Add driver for SPI controller of PCI1XXXX PCIe switch")
Signed-off-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
---
drivers/spi/spi-pci1xxxx.c | 17 +++++------------
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/drivers/spi/spi-pci1xxxx.c b/drivers/spi/spi-pci1xxxx.c
index 82d4bfeea1fa..4445d82409d6 100644
--- a/drivers/spi/spi-pci1xxxx.c
+++ b/drivers/spi/spi-pci1xxxx.c
@@ -114,17 +114,14 @@ static void pci1xxxx_spi_set_cs(struct spi_device *spi, bool enable)
/* Set the DEV_SEL bits of the SPI_MST_CTL_REG */
regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
- if (enable) {
+ if (!enable) {
+ regval |= SPI_FORCE_CE;
regval &= ~SPI_MST_CTL_DEVSEL_MASK;
regval |= (spi_get_chipselect(spi, 0) << 25);
- writel(regval,
- par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
} else {
- regval &= ~(spi_get_chipselect(spi, 0) << 25);
- writel(regval,
- par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
-
+ regval &= ~SPI_FORCE_CE;
}
+ writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
}
static u8 pci1xxxx_get_clock_div(u32 hz)
@@ -199,7 +196,7 @@ static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr,
else
regval &= ~SPI_MST_CTL_MODE_SEL;
- regval |= ((clkdiv << 5) | SPI_FORCE_CE);
+ regval |= (clkdiv << 5);
regval &= ~SPI_MST_CTL_CMD_LEN_MASK;
regval |= (len << 8);
writel(regval, par->reg_base +
@@ -223,10 +220,6 @@ static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr,
}
}
}
-
- regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
- regval &= ~SPI_FORCE_CE;
- writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
p->spi_xfer_in_progress = false;
return 0;
--
2.25.1
next prev parent reply other threads:[~2023-04-04 17:17 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-04 17:16 [PATCH SPI for-next 0/3] spi: mchp-pci1xxxx: Fix minor bugs in spi-pci1xxxx driver Tharun Kumar P
2023-04-04 17:16 ` [PATCH SPI for-next 1/3] spi: mchp-pci1xxxx: Fix length of SPI transactions not set properly in driver Tharun Kumar P
2023-04-04 17:16 ` [PATCH SPI for-next 2/3] spi: mchp-pci1xxxx: Fix SPI transactions not working after suspend and resume Tharun Kumar P
2023-04-04 17:16 ` Tharun Kumar P [this message]
2023-04-05 13:43 ` [PATCH SPI for-next 0/3] spi: mchp-pci1xxxx: Fix minor bugs in spi-pci1xxxx driver Mark Brown
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