From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53672E82CA2 for ; Wed, 27 Sep 2023 14:54:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232248AbjI0Oyv (ORCPT ); Wed, 27 Sep 2023 10:54:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232100AbjI0Oyv (ORCPT ); Wed, 27 Sep 2023 10:54:51 -0400 Received: from relay1-d.mail.gandi.net (relay1-d.mail.gandi.net [217.70.183.193]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49ABFF4 for ; Wed, 27 Sep 2023 07:54:50 -0700 (PDT) Received: by mail.gandi.net (Postfix) with ESMTPSA id 1F837240013; Wed, 27 Sep 2023 14:54:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1695826488; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bU7T7dDQ/dHFd7LrSzq4NNGKbKWAKTZ4mfNpbgF6ZUs=; b=bh26dm8STTmIX6aEY3yids5BNROji9NHQGCOkljcLJGC7bWQN0oVyOYBbPx8EDjBWSUOhI kZlgWMO10lk3atwHM1kAVX27i0xASK7A1e+nfUzrjb2Xg6uNXXXTu++hyN2wXoU7cwNdy0 hFIpSIr3igF9xMGLltEJ8R9cP7nRW3LXTxsocJd9Ha+COgsVI+DmGUQFre4pi0hPCf6uuO 81rLsrDdebLX/bqTcmFAiWGh2863Q5KfTaG3AUzOKMKt4N1HCzB9QKh2kRgmINHh6GLOkE yK+sCCVNwpUWbTpGLujlpRxy+fiuTIx5/uIV9fENKj3PD9H0dzqZ5YAOtT8TYw== Date: Wed, 27 Sep 2023 16:54:38 +0200 From: Miquel Raynal To: Mark Brown Cc: "Usyskin, Alexander" , "Winkler, Tomas" , Richard Weinberger , Vignesh Raghavendra , Jani Nikula , Joonas Lahtinen , "Vivi, Rodrigo" , "Lubart, Vitaly" , "linux-mtd@lists.infradead.org" , "intel-gfx@lists.freedesktop.org" , Tudor Ambarus , Pratyush Yadav , Michael Walle , "linux-spi@vger.kernel.org" Subject: Re: [PATCH 00/10] drm/i915/spi: spi access for discrete graphics Message-ID: <20230927165350.470bea0f@xps-13> In-Reply-To: References: <0d60a78b-0305-4cb3-babe-4eefe5001b29@sirena.org.uk> <20230912152102.0dfe7558@xps-13> <1b93fffe-5aac-42f3-9bbe-a307758673cf@sirena.org.uk> <0682443d-5219-4aa2-a932-ee3e04c0760e@sirena.org.uk> Organization: Bootlin X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: miquel.raynal@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Hi Mark, broonie@kernel.org wrote on Wed, 27 Sep 2023 16:37:35 +0200: > On Wed, Sep 27, 2023 at 02:11:47PM +0000, Usyskin, Alexander wrote: >=20 > > There is a Discreet Graphic device with embedded SPI (controller & flas= h). > > The embedded SPI is not visible to OS. > > There is another HW in the chip that gates access to the controller and > > exposes registers for: > > region select; read and write (4 and 8 bytes); erase (4K); error regist= er; =20 >=20 > So assuming that's flash region select it sounds like this is a MTD > controller and the fact that there's SPI isn't really relevant at all > from a programming model point of view and it should probably be > described as a MTD controller of some kind. Does that sound about > right? Yeah in this case it seems the best option if the OS only has access to a very small subset of what the spi controller can do. Thanks, Miqu=C3=A8l