From: AlvinZhou <alvinzhou.tw@gmail.com>
To: linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org,
linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org,
pratyush@kernel.org, mwalle@kernel.org,
miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
broonie@kernel.org
Cc: chengminglin@mxic.com.tw, leoyu@mxic.com.tw,
AlvinZhou <alvinzhou@mxic.com.tw>,
JaimeLiao <jaimeliao@mxic.com.tw>
Subject: [PATCH v9 3/6] mtd: spi-nor: core: Allow specifying the byte order in Octal DTR mode
Date: Thu, 18 Jul 2024 11:46:11 +0800 [thread overview]
Message-ID: <20240718034614.484018-4-alvinzhou.tw@gmail.com> (raw)
In-Reply-To: <20240718034614.484018-1-alvinzhou.tw@gmail.com>
From: AlvinZhou <alvinzhou@mxic.com.tw>
From: Tudor Ambarus <tudor.ambarus@linaro.org>
Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR.
The byte order of 16-bit words is swapped when read or written in 8D-8D-8D
mode compared to STR modes. Allow operations to specify the byte order in
DTR mode, so that controllers can swap the bytes back at run-time to
address the flash's endianness requirements, if they are capable. If the
controller is not capable of swapping the bytes, the protocol is downgrade
via spi_nor_spimem_adjust_hwcaps(). When available, the swapping of the
bytes is always done regardless if it's a data or register access, so that
it comply with the JESD216 requirements: "Byte order of 16-bit words is
swapped when read in 8D-8D-8D mode compared to 1-1-1".
Merge Tudor's patch and add modifications for suiting newer version
of Linux kernel.
Suggested-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw>
---
drivers/mtd/spi-nor/core.c | 4 ++++
drivers/mtd/spi-nor/core.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 028514c6996f..31f57b17023f 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -113,6 +113,10 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor,
op->cmd.opcode = (op->cmd.opcode << 8) | ext;
op->cmd.nbytes = 2;
}
+
+ /* SWAP16 is only applicable when Octal DTR mode */
+ if (proto == SNOR_PROTO_8_8_8_DTR && nor->flags & SNOR_F_SWAP16)
+ op->data.swap16 = true;
}
/**
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 442786685515..baf6c4b5912b 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -140,6 +140,7 @@ enum spi_nor_option_flags {
SNOR_F_RWW = BIT(14),
SNOR_F_ECC = BIT(15),
SNOR_F_NO_WP = BIT(16),
+ SNOR_F_SWAP16 = BIT(17),
};
struct spi_nor_read_command {
--
2.25.1
next prev parent reply other threads:[~2024-07-18 3:47 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-18 3:46 [PATCH v9 0/6] Add octal DTR support for Macronix flash AlvinZhou
2024-07-18 3:46 ` [PATCH v9 1/6] mtd: spi-nor: add Octal " AlvinZhou
2024-07-18 3:46 ` [PATCH v9 2/6] spi: spi-mem: Allow specifying the byte order in Octal DTR mode AlvinZhou
2024-09-24 11:37 ` Mark Brown
2024-07-18 3:46 ` AlvinZhou [this message]
2024-07-18 3:46 ` [PATCH v9 4/6] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT AlvinZhou
2024-07-18 3:46 ` [PATCH v9 5/6] spi: mxic: Add support for swapping byte AlvinZhou
2024-09-24 11:38 ` Mark Brown
2024-09-24 14:29 ` Tudor Ambarus
2024-09-24 14:52 ` Mark Brown
2024-09-25 6:22 ` Tudor Ambarus
2024-07-18 3:46 ` [PATCH v9 6/6] mtd: spi-nor: add support for Macronix Octal flash AlvinZhou
2024-09-23 6:53 ` Tudor Ambarus
2024-09-23 7:18 ` Michael Walle
2024-09-24 3:25 ` Alvin Zhou
2024-09-24 6:26 ` Tudor Ambarus
2024-09-24 6:36 ` Tudor Ambarus
2024-09-24 7:17 ` Tudor Ambarus
2024-09-25 9:57 ` Miquel Raynal
2024-09-26 3:06 ` Alvin Zhou
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