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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SA2PEPF00003AEA.mail.protection.outlook.com (10.167.248.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8005.15 via Frontend Transport; Wed, 25 Sep 2024 13:39:53 +0000 Received: from airavat.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 25 Sep 2024 08:39:51 -0500 From: Raju Rangoju To: , CC: , , , , Subject: [PATCH V2 0/8] spi: spi_amd: Performance Optimization Patch Series Date: Wed, 25 Sep 2024 19:06:36 +0530 Message-ID: <20240925133644.2922359-1-Raju.Rangoju@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Sep 2024 13:39:53.7903 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 15860e59-7e44-44cd-5d80-08dcdd67898a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AEA.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6104 AMD SPI controller’s index mode performance is constrained by the hardware limitation of the FIFO queue length. This patch series introduces optimizations to the spi_amd driver, aiming to maximize throughput and enhance overall performance. The changes includes, - Enable SPI dual and quad I/O modes and update SPI-MEM support function to reflect AMD SPI0 hardware capabilities. - Utilize efficient kernel APIs to streamline SPI I/O operations for enhanced performance. - Refine the set tx/rx count functions to optimize SPI I/O throughput. - Minimize the number of data read calls by efficiently retrieving data from FIFO queues, improving SPI I/O efficiency. - Add changes to support AMD HID2 SPI controller and update SPI-MEM support function to reflect AMD HID2 hardware capabilities. - Add changes to set SPI controller address mode before initiating the commands - Add changes to implement HIDDMA read operation support for HID2 SPI controller V1->V2: ------- - Eliminate the separate patch that introduces SPI-MEM support function modifications, and incorporate those changes into the existing patches for enabling dual and quad I/O modes, as well as enhance support for the HID2 SPI controller. Raju Rangoju (8): spi: spi_amd: Sort headers alphabetically spi: spi_amd: Enable dual and quad I/O modes spi: spi_amd: Replace ioread/iowrite calls spi: spi_amd: Updates to set tx/rx count functions spi: spi_amd: Optimize IO operations spi: spi_amd: Add support for HID2 SPI controller spi: spi_amd: Set controller address mode spi: spi_amd: Add HIDDMA basic read support drivers/spi/spi-amd.c | 325 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 295 insertions(+), 30 deletions(-) -- 2.34.1