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From: Vishwaroop A <va@nvidia.com>
To: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
	<skomatineni@nvidia.com>, <ldewangan@nvidia.com>,
	<broonie@kernel.org>, <linux-spi@vger.kernel.org>,
	<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<kyarlagadda@nvidia.com>, <smangipudi@nvidia.com>
Cc: <va@nvidia.com>
Subject: [PATCH v2 5/6] spi: tegra210-quad: modify chip select (CS) deactivation
Date: Wed, 12 Feb 2025 14:46:50 +0000	[thread overview]
Message-ID: <20250212144651.2433086-6-va@nvidia.com> (raw)
In-Reply-To: <20250212144651.2433086-1-va@nvidia.com>

Modify the chip select (CS) deactivation and inter-transfer delay
execution to be performed only during the DATA_TRANSFER phase when
the cs_change flag is not set. This ensures proper CS handling and
timing between transfers while eliminating redundant operations.

Fixes: 1b8342cc4a38 ("spi: tegra210-quad: combined sequence mode")

Signed-off-by: Vishwaroop A <va@nvidia.com>
---
 drivers/spi/spi-tegra210-quad.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c
index 2d7a2e3da337..04f41e92c1e2 100644
--- a/drivers/spi/spi-tegra210-quad.c
+++ b/drivers/spi/spi-tegra210-quad.c
@@ -1171,16 +1171,16 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
 				ret = -EIO;
 				goto exit;
 			}
-			if (!xfer->cs_change) {
-				tegra_qspi_transfer_end(spi);
-				spi_transfer_delay_exec(xfer);
-			}
 			break;
 		default:
 			ret = -EINVAL;
 			goto exit;
 		}
 		msg->actual_length += xfer->len;
+		if (!xfer->cs_change && transfer_phase == DATA_TRANSFER) {
+			tegra_qspi_transfer_end(spi);
+			spi_transfer_delay_exec(xfer);
+		}
 		transfer_phase++;
 	}
 	ret = 0;
-- 
2.17.1


  parent reply	other threads:[~2025-02-12 14:47 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-03  6:04 [PATCH 0/6] Configure Clocks, Add Native Dma support Vishwaroop A
2025-01-03  6:04 ` [PATCH V1 1/6] arm64: tegra: Configure QSPI clocks and add DMA Vishwaroop A
2025-01-09 10:40   ` Thierry Reding
2025-02-12 14:39     ` Vishwaroop A
2025-03-07 13:28       ` Jon Hunter
2025-02-12 14:46     ` [PATCH v2 0/6] Configure Clocks, Add Native Dma support Vishwaroop A
2025-02-12 14:46       ` [PATCH v2 1/6] arm64: tegra: Configure QSPI clocks and add DMA Vishwaroop A
2025-02-27 10:39         ` Thierry Reding
2025-02-27 11:13         ` Jon Hunter
2025-02-12 14:46       ` [PATCH v2 2/6] spi: tegra210-quad: Update dummy sequence configuration Vishwaroop A
2025-02-27 10:42         ` Thierry Reding
2025-02-12 14:46       ` [PATCH v2 3/6] spi: tegra210-quad: Fix X1_X2_X4 encoding and support x4 transfers Vishwaroop A
2025-02-27 10:45         ` Thierry Reding
2025-02-12 14:46       ` [PATCH v2 4/6] spi: tegra210-quad: remove redundant error handling code Vishwaroop A
2025-02-27 10:45         ` Thierry Reding
2025-02-12 14:46       ` Vishwaroop A [this message]
2025-02-27 10:46         ` [PATCH v2 5/6] spi: tegra210-quad: modify chip select (CS) deactivation Thierry Reding
2025-02-12 14:46       ` [PATCH v2 6/6] spi: tegra210-quad: Introduce native DMA support Vishwaroop A
2025-02-27 11:14         ` Thierry Reding
2025-02-27 11:17         ` Jon Hunter
2025-02-12 22:08       ` [PATCH v2 0/6] Configure Clocks, Add Native Dma support Rob Herring (Arm)
2025-02-27 11:09       ` Jon Hunter
2025-01-03  6:04 ` [PATCH V1 2/6] spi: tegra210-quad: Update dummy sequence configuration Vishwaroop A
2025-01-03  6:04 ` [PATCH V1 3/6] spi: tegra210-quad: Fix X1_X2_X4 encoding and support x4 transfers Vishwaroop A
2025-01-03  6:04 ` [PATCH V1 4/6] spi: tegra210-quad: remove redundant error handling code Vishwaroop A
2025-01-03  6:04 ` [PATCH V1 5/6] spi: tegra210-quad: modify chip select (CS) deactivation Vishwaroop A
2025-01-03  6:04 ` [PATCH V1 6/6] spi: tegra210-quad: Introduce native DMA support Vishwaroop A
2025-01-03 14:21   ` kernel test robot
2025-01-03 23:16   ` kernel test robot
2025-01-06 13:04   ` Mark Brown

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