From: James Clark <james.clark@linaro.org>
To: Vladimir Oltean <olteanv@gmail.com>,
Mark Brown <broonie@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Frank Li <Frank.Li@nxp.com>,
Chester Lin <chester62515@gmail.com>,
Matthias Brugger <mbrugger@suse.com>,
Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>,
NXP S32 Linux Team <s32@nxp.com>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
larisa.grigore@nxp.com, arnd@linaro.org,
andrei.stefanescu@nxp.com, dan.carpenter@linaro.org
Cc: linux-spi@vger.kernel.org, imx@lists.linux.dev,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
"Radu Pirea (NXP OSS)" <radu-nicolae.pirea@oss.nxp.com>,
Larisa Grigore <Larisa.Grigore@nxp.com>,
James Clark <james.clark@linaro.org>
Subject: [PATCH 14/14] arm64: dts: Add DSPI entries for S32G platforms
Date: Fri, 09 May 2025 12:06:01 +0100 [thread overview]
Message-ID: <20250509-james-nxp-spi-v1-14-32bfcd2fea11@linaro.org> (raw)
In-Reply-To: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org>
From: Larisa Grigore <larisa.grigore@nxp.com>
S32G3 and S32G2 have the same 6 SPI devices, add the DT entries. Devices
are all the same except spi0 has 8 chip selects instead of 5. Clock
settings for the chip rely on ATF Firmware [1].
[1]: https://github.com/nxp-auto-linux/arm-trusted-firmware
Co-developed-by: Radu Pirea (NXP OSS) <radu-nicolae.pirea@oss.nxp.com>
Signed-off-by: Radu Pirea (NXP OSS) <radu-nicolae.pirea@oss.nxp.com>
Signed-off-by: Larisa Grigore <Larisa.Grigore@nxp.com>
Signed-off-by: James Clark <james.clark@linaro.org>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 78 ++++++++++++++++++++++
arch/arm64/boot/dts/freescale/s32g3.dtsi | 78 ++++++++++++++++++++++
arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi | 87 +++++++++++++++++++++++++
arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi | 77 ++++++++++++++++++++++
4 files changed, 320 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index ea1456d361a3..68848575bf81 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -376,6 +376,45 @@ uart1: serial@401cc000 {
status = "disabled";
};
+ spi0: spi@401d4000 {
+ compatible = "nxp,s32g2-dspi";
+ reg = <0x401d4000 0x1000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 26>;
+ clock-names = "dspi";
+ spi-num-chipselects = <8>;
+ bus-num = <0>;
+ dmas = <&edma0 0 7>, <&edma0 0 8>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi1: spi@401d8000 {
+ compatible = "nxp,s32g2-dspi";
+ reg = <0x401d8000 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 26>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <1>;
+ dmas = <&edma0 0 10>, <&edma0 0 11>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi2: spi@401dc000 {
+ compatible = "nxp,s32g2-dspi";
+ reg = <0x401dc000 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 26>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <2>;
+ dmas = <&edma0 0 13>, <&edma0 0 14>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
i2c0: i2c@401e4000 {
compatible = "nxp,s32g2-i2c";
reg = <0x401e4000 0x1000>;
@@ -460,6 +499,45 @@ uart2: serial@402bc000 {
status = "disabled";
};
+ spi3: spi@402c8000 {
+ compatible = "nxp,s32g2-dspi";
+ reg = <0x402c8000 0x1000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 26>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <3>;
+ dmas = <&edma0 1 7>, <&edma0 1 8>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi4: spi@402cc000 {
+ compatible = "nxp,s32g2-dspi";
+ reg = <0x402cc000 0x1000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 26>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <4>;
+ dmas = <&edma0 1 10>, <&edma0 1 11>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi5: spi@402d0000 {
+ compatible = "nxp,s32g2-dspi";
+ reg = <0x402d0000 0x1000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 26>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <5>;
+ dmas = <&edma0 1 13>, <&edma0 1 14>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
i2c3: i2c@402d8000 {
compatible = "nxp,s32g2-i2c";
reg = <0x402d8000 0x1000>;
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index 991dbfbfa203..4f883b1a50ad 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -435,6 +435,45 @@ uart1: serial@401cc000 {
status = "disabled";
};
+ spi0: spi@401d4000 {
+ compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
+ reg = <0x401d4000 0x1000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 26>;
+ clock-names = "dspi";
+ spi-num-chipselects = <8>;
+ bus-num = <0>;
+ dmas = <&edma0 0 7>, <&edma0 0 8>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi1: spi@401d8000 {
+ compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
+ reg = <0x401d8000 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 26>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <1>;
+ dmas = <&edma0 0 10>, <&edma0 0 11>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi2: spi@401dc000 {
+ compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
+ reg = <0x401dc000 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 26>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <2>;
+ dmas = <&edma0 0 13>, <&edma0 0 14>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
i2c0: i2c@401e4000 {
compatible = "nxp,s32g3-i2c",
"nxp,s32g2-i2c";
@@ -524,6 +563,45 @@ uart2: serial@402bc000 {
status = "disabled";
};
+ spi3: spi@402c8000 {
+ compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
+ reg = <0x402c8000 0x1000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 26>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <3>;
+ dmas = <&edma0 1 7>, <&edma0 1 8>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi4: spi@402cc000 {
+ compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
+ reg = <0x402cc000 0x1000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 26>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <4>;
+ dmas = <&edma0 1 10>, <&edma0 1 11>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi5: spi@402d0000 {
+ compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
+ reg = <0x402d0000 0x1000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 26>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <5>;
+ dmas = <&edma0 1 13>, <&edma0 1 14>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
i2c3: i2c@402d8000 {
compatible = "nxp,s32g3-i2c",
"nxp,s32g2-i2c";
diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
index d26af0fb8be7..812b37b0098b 100644
--- a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
@@ -173,6 +173,77 @@ i2c4-gpio-grp1 {
pinmux = <0x2d40>, <0x2d30>;
};
};
+
+ dspi1_pins: dspi1_pins {
+ dspi1_grp0 {
+ pinmux = <0x72>;
+ output-enable;
+ input-enable;
+ slew-rate = <150>;
+ bias-pull-up;
+ };
+
+ dspi1_grp1 {
+ pinmux = <0x62>;
+ output-enable;
+ slew-rate = <150>;
+ };
+
+ dspi1_grp2 {
+ pinmux = <0x83>;
+ output-enable;
+ input-enable;
+ slew-rate = <150>;
+ };
+
+ dspi1_grp3 {
+ pinmux = <0x5F0>;
+ input-enable;
+ slew-rate = <150>;
+ bias-pull-up;
+ };
+
+ dspi1_grp4 {
+ pinmux = <0x3D92>,
+ <0x3DA2>,
+ <0x3DB2>;
+ };
+ };
+
+ dspi5_pins: dspi5_pins {
+ dspi5_grp0 {
+ pinmux = <0x93>;
+ output-enable;
+ input-enable;
+ slew-rate = <150>;
+ };
+
+ dspi5_grp1 {
+ pinmux = <0xA0>;
+ input-enable;
+ slew-rate = <150>;
+ bias-pull-up;
+ };
+
+ dspi5_grp2 {
+ pinmux = <0x3ED2>,
+ <0x3EE2>,
+ <0x3EF2>;
+ };
+
+ dspi5_grp3 {
+ pinmux = <0xB3>;
+ output-enable;
+ slew-rate = <150>;
+ };
+ dspi5_grp4 {
+ pinmux = <0xC3>;
+ output-enable;
+ input-enable;
+ slew-rate = <150>;
+ bias-pull-up;
+ };
+ };
};
&can0 {
@@ -220,3 +291,19 @@ &i2c4 {
pinctrl-1 = <&i2c4_gpio_pins>;
status = "okay";
};
+
+&spi1 {
+ pinctrl-0 = <&dspi1_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ spidev0: spidev@0 {
+ compatible = "rohm,dh2228fv";
+ spi-max-frequency = <4000000>;
+ reg = <0>;
+ fsl,spi-cs-sck-delay = <100>;
+ fsl,spi-sck-cs-delay = <100>;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
index ba53ec622f0b..798b58fa9536 100644
--- a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
@@ -127,6 +127,77 @@ i2c4-gpio-grp1 {
pinmux = <0x2d40>, <0x2d30>;
};
};
+
+ dspi1_pins: dspi1_pins {
+ dspi1_grp0 {
+ pinmux = <0x62>;
+ output-enable;
+ slew-rate = <150>;
+ };
+
+ dspi1_grp1 {
+ pinmux = <0x72>;
+ output-enable;
+ input-enable;
+ slew-rate = <150>;
+ bias-pull-up;
+ };
+
+ dspi1_grp2 {
+ pinmux = <0x83>;
+ output-enable;
+ input-enable;
+ slew-rate = <150>;
+ };
+
+ dspi1_grp3 {
+ pinmux = <0x5F0>;
+ input-enable;
+ slew-rate = <150>;
+ bias-pull-up;
+ };
+
+ dspi1_grp4 {
+ pinmux = <0x3D92>,
+ <0x3DA2>,
+ <0x3DB2>;
+ };
+ };
+
+ dspi5_pins: dspi5_pins {
+ dspi5_grp0 {
+ pinmux = <0x93>;
+ output-enable;
+ input-enable;
+ slew-rate = <150>;
+ };
+
+ dspi5_grp1 {
+ pinmux = <0xA0>;
+ input-enable;
+ slew-rate = <150>;
+ bias-pull-up;
+ };
+
+ dspi5_grp2 {
+ pinmux = <0x3ED2>,
+ <0x3EE2>,
+ <0x3EF2>;
+ };
+
+ dspi5_grp3 {
+ pinmux = <0xB3>;
+ output-enable;
+ slew-rate = <150>;
+ };
+ dspi5_grp4 {
+ pinmux = <0xC3>;
+ output-enable;
+ input-enable;
+ slew-rate = <150>;
+ bias-pull-up;
+ };
+ };
};
&can0 {
@@ -155,6 +226,12 @@ pcal6524: gpio-expander@22 {
};
};
+&spi1 {
+ pinctrl-0 = <&dspi1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&i2c2 {
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c2_pins>;
--
2.34.1
next prev parent reply other threads:[~2025-05-09 11:07 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-09 11:05 [PATCH 00/14] spi: spi-fsl-dspi: DSPI support for NXP S32G platforms James Clark
2025-05-09 11:05 ` [PATCH 01/14] spi: spi-fsl-dspi: Define regmaps per device James Clark
2025-05-09 16:04 ` Vladimir Oltean
2025-05-09 11:05 ` [PATCH 02/14] spi: spi-fsl-dspi: Re-use one volatile regmap for both device types James Clark
2025-05-09 16:07 ` Vladimir Oltean
2025-05-09 11:05 ` [PATCH 03/14] spi: spi-fsl-dspi: restrict register range for regmap access James Clark
2025-05-09 14:06 ` Vladimir Oltean
2025-05-19 10:25 ` James Clark
2025-05-10 1:16 ` Mark Brown
2025-05-09 11:05 ` [PATCH 04/14] spi: spi-fsl-dspi: Add config and regmaps for S32G platforms James Clark
2025-05-09 11:05 ` [PATCH 05/14] spi: spi-fsl-dspi: Use spi_alloc_target for target James Clark
2025-05-09 11:05 ` [PATCH 06/14] spi: spi-fsl-dspi: Avoid setup_accel logic for DMA transfers James Clark
2025-05-09 11:05 ` [PATCH 07/14] spi: spi-fsl-dspi: Reset SR flags before sending a new message James Clark
2025-05-09 11:05 ` [PATCH 08/14] spi: spi-fsl-dspi: Use DMA for S32G controller in target mode James Clark
2025-05-09 11:05 ` [PATCH 09/14] spi: spi-fsl-dspi: Reinitialize DSPI regs after resuming for S32G James Clark
2025-05-09 11:05 ` [PATCH 10/14] spi: spi-fsl-dspi: Enable modified transfer protocol James Clark
2025-05-10 1:18 ` Mark Brown
2025-05-15 12:20 ` James Clark
2025-05-09 11:05 ` [PATCH 11/14] spi: spi-fsl-dspi: Halt the module after a new message transfer James Clark
2025-05-10 1:19 ` Mark Brown
2025-05-09 11:05 ` [PATCH 12/14] dt-bindings: spi: dspi: Add S32G support James Clark
2025-05-09 11:14 ` Krzysztof Kozlowski
2025-05-09 11:26 ` James Clark
2025-05-09 11:06 ` [PATCH 13/14] spi: spi-fsl-dspi: Enable support for S32G platforms James Clark
2025-05-09 11:06 ` James Clark [this message]
2025-05-09 11:26 ` [PATCH 14/14] arm64: dts: Add DSPI entries " Krzysztof Kozlowski
2025-05-09 12:54 ` Matti Vaittinen
2025-05-09 13:46 ` James Clark
2025-05-09 13:57 ` Krzysztof Kozlowski
2025-05-09 14:17 ` [PATCH 00/14] spi: spi-fsl-dspi: DSPI support for NXP " Rob Herring (Arm)
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