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From: Vladimir Oltean <vladimir.oltean@nxp.com>
To: James Clark <james.clark@linaro.org>
Cc: Vladimir Oltean <olteanv@gmail.com>,
	Mark Brown <broonie@kernel.org>,
	linux-spi@vger.kernel.org, imx@lists.linux.dev,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/4] spi: spi-fsl-dspi: Clear completion counter before initiating transfer
Date: Wed, 11 Jun 2025 00:31:20 +0300	[thread overview]
Message-ID: <20250610213120.ib5tkbh4xu7af4jr@skbuf> (raw)
In-Reply-To: <20250610210147.kwuwwjtcl36hrxjc@skbuf>

On Wed, Jun 11, 2025 at 12:01:47AM +0300, Vladimir Oltean wrote:
> On Tue, Jun 10, 2025 at 04:41:04PM +0100, James Clark wrote:
> > On 10/06/2025 12:34 pm, Vladimir Oltean wrote:
> > > On Mon, Jun 09, 2025 at 04:32:38PM +0100, James Clark wrote:
> > > > In target mode, extra interrupts can be received between the end of a
> > > > transfer and halting the module if the host continues sending more data.
> > > 
> > > Presumably you mean not just any extra interrupts can be received, but
> > > specifically CMDTCF, since that triggers the complete(&dspi->xfer_done)
> > > call. Other interrupt sources are masked in XSPI mode and should be
> > > irrelevant.
> > 
> > Yes complete(&dspi->xfer_done) is called so CMDTCF is set. For example in
> > one case of underflow I get SPI_SR = 0xca8b0450, which is these flags:
> > 
> >   TCF, TXRXS, TFUF, TFFF, CMDTCF, RFOF, RFDF, CMDFFF
> > 
> > Compared to a successful transfer I get 0xc2830330:
> > 
> >   TCF, TXRXS,       TFFF, CMDTCF,       RFDF, CMDFFF
> 
> Ok, so my new question would be: if CMDTCF is set, presumably it means a
> command was transferred. What command was transferred, and who put data
> in the FIFO for it?
> 
> Because the answer to the above is AFAIU "no one", I guess the driver
> should ignore CMDTCF when TFUF (TX FIFO underflow) is set; I consider
> that to be the logic bug. You are also doing that in patch 4/4, except
> you still call complete() for some reason. If you don't call complete(),
> there is no reason to fend against spurious completions.
> 
> I think I would prefer seeing more deliberate decisions in the driver,
> it helps if things don't just work by coincidence.

After thinking some more, I think I agree with your decision.

If there's a TX FIFO underflow in target mode, presumably there are 2
cases to handle.

1. The underflow occurred in the middle of a large-ish SPI message
   prepared by the driver, where the driver couldn't refill the TX FIFO
   fast enough in dspi_interrupt().

2. The underflow occurred because the driver had absolutely no SPI
   message prepared, and yet the host wanted something.

What changed my mind is that if you don't call complete() on SPI_SR_TFUF
(like I suggested), then case #1 above will hang. Your proposal is to
call complete() anyway, but to discard any previous completions,
associated with case #2, when there's a new message to prepare.

But I would like you to introduce a comment above the earlier
reinit_completion() explaining why it is there.

  reply	other threads:[~2025-06-10 21:31 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-09 15:32 [PATCH 0/4] spi: spi-fsl-dspi: Target mode improvements James Clark
2025-06-09 15:32 ` [PATCH 1/4] spi: spi-fsl-dspi: Clear completion counter before initiating transfer James Clark
2025-06-10 11:34   ` Vladimir Oltean
2025-06-10 15:41     ` James Clark
2025-06-10 21:01       ` Vladimir Oltean
2025-06-10 21:31         ` Vladimir Oltean [this message]
2025-06-11  9:12           ` James Clark
2025-06-09 15:32 ` [PATCH 2/4] spi: spi-fsl-dspi: Use non-coherent memory for DMA James Clark
2025-06-10  8:26   ` Arnd Bergmann
2025-06-10  9:03     ` James Clark
2025-06-10 15:15   ` Frank Li
2025-06-10 15:46     ` James Clark
2025-06-13 15:56       ` David Laight
2025-06-10 15:48     ` Arnd Bergmann
2025-06-10 15:56       ` Frank Li
2025-06-11  9:01         ` Vladimir Oltean
2025-06-12 11:05           ` James Clark
2025-06-12 11:15             ` Vladimir Oltean
2025-06-12 14:14               ` James Clark
2025-06-12 14:23                 ` Vladimir Oltean
2025-06-12 14:28                   ` James Clark
2025-06-12 14:31                     ` Vladimir Oltean
2025-06-12 14:35                       ` James Clark
2025-06-12 14:36                 ` Vladimir Oltean
2025-06-12 15:36                   ` James Clark
2025-06-12 15:37                     ` James Clark
2025-06-12 14:43                 ` Mark Brown
2025-06-12 15:47                   ` James Clark
2025-06-12 15:51                     ` Vladimir Oltean
2025-06-12 15:40                 ` Arnd Bergmann
2025-06-12 11:15             ` Arnd Bergmann
2025-06-09 15:32 ` [PATCH 3/4] spi: spi-fsl-dspi: Increase DMA buffer size James Clark
2025-06-09 15:32 ` [PATCH 4/4] spi: spi-fsl-dspi: Report FIFO overflows as errors James Clark
2025-06-10 21:52   ` Vladimir Oltean
2025-06-11 14:40     ` James Clark
2025-06-11 14:56       ` Vladimir Oltean
2025-06-11 15:00         ` James Clark
2025-06-30 11:40 ` [PATCH 0/4] spi: spi-fsl-dspi: Target mode improvements Mark Brown
2025-06-30 12:23   ` James Clark
2025-06-30 12:25     ` Mark Brown
2025-06-30 12:36       ` James Clark
2025-06-30 12:40         ` Mark Brown
2025-06-30 12:54           ` James Clark

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