From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-177.mta1.migadu.com (out-177.mta1.migadu.com [95.215.58.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44BD123AE87 for ; Mon, 16 Jun 2025 22:01:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.177 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111290; cv=none; b=XT0n/rsuS3qlKXRxleiPnO//V+wCOuqw2Ivqdpw178+jmTD7GxhCI9VcOtvdy4Z1YYfOtoGiCMv31ypuwE3JbRWLHfSTYrD+vVHIBWj8Wq2InJFgjK3FiSjGQa4bXpTl6n9EUNxHV70vOxzSOGdHwCRq2Mo3PZUAclE0ryclz4w= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111290; c=relaxed/simple; bh=St4IBqo9GKAYO2mEkfVIKVeAl+IZzHIvMD4FgFkoR4o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bTbpE7zPU8TH8QcwKxqqNPa+ydJZHHJmldthZXMy8g6OqjSC/A3e3dNM6ElK155BhAGqd8IPfwIWWUtpgjn/2PSZQoG/nE0M+fVUloZGNg8gHFrb18micD8vYiln2fuAurgev/LrGP8Z8d+ewXn18027qYJAdaT06DpGPSMzeb0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=EqtSoBDA; arc=none smtp.client-ip=95.215.58.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="EqtSoBDA" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750111286; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=baIhgE/N38Lr9mmVCwKX0SXbBt/r7eLwevkwAfS0a18=; b=EqtSoBDAhVsc11UmSbE01aj/EmNvOXXZu5gS7VXEGDDNz4D+TobMSEaQ6RA10sZeDGgKYZ MHjLl4dQaiKRo6DjwxEIUpfEIuoZp5+PIkToBDNsZM+GrF/q8HmAhmBiU6LPOiZnjggmKc ycVP8hhm8oqBGMXYMLJzYeYOInrwe+4= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , Miquel Raynal , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Lechner , Amit Kumar Mahapatra , Sean Anderson , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v2 9/9] ARM64: xilinx: zynqmp: Add spi-buses property Date: Mon, 16 Jun 2025 18:00:54 -0400 Message-Id: <20250616220054.3968946-10-sean.anderson@linux.dev> In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev> References: <20250616220054.3968946-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT Add the spi-buses property to the ZynqMP devicetrees. This is pretty simple, since all boards use the lower bus. Signed-off-by: Sean Anderson --- (no changes since v1) arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 1 + 10 files changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index bfa7ea6b9224..3d3cb656f38c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -132,6 +132,7 @@ &qspi { /* MIO 0-5 - U143 */ spi_flash: flash@0 { /* MT25QU512A */ compatible = "jedec,spi-nor"; /* 64MB */ reg = <0>; + spi-buses = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts index 3dec57cf18be..f550ccea58cd 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts @@ -45,6 +45,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; + spi-buses = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index 6aff22d43361..4ad5efdd40cd 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -359,6 +359,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; + spi-buses = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts index 6ec1d9813973..26c33685b320 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -177,6 +177,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; + spi-buses = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 7e26489a1539..aa4ed3a082fa 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -958,6 +958,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; + spi-buses = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index eb2090673ec1..acbe0758a31b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -444,6 +444,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; + spi-buses = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 4694d0a841f1..9b0324acbeec 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -456,6 +456,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; + spi-buses = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 7beedd730f94..fd983f4c416d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -964,6 +964,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; + spi-buses = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index b67ff7ecf3c3..af225413a274 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -794,6 +794,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; + spi-buses = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts index a38c2baeba6c..65790e341c15 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts @@ -47,6 +47,7 @@ &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; reg = <0x0>; + spi-buses = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; -- 2.35.1.1320.gc452695387.dirty