[PATCH v3 0/3] spi: atmel: Add GCLK support and simplify MR update

[Manikandan Muralidharan <manikandan.m@microchip.com>]

This patch series introduces support for using the Generic Clock (GCLK)
as a clock source in the Atmel SPI controller, and also includes a small
cleanup to simplify MR register handling in cs_activate().

On platforms like the SAM9X7 SoC, the SPI peripheral clock can run at
266 MHz. This can exceed the maximum value supported by the Serial Clock
Baud Rate (SCBR) divider, leading to SPI transfer failures. To address
this, the Atmel SPI controller can use an alternate clock source — the
Generic Clock (GCLK) — for SPCK generation.

--------
changes in v3:
- Add cover letter
- 2/3 - add explanation for the spi_gclk addition

changes in v2:
- 1/3 - Fixed mail threading
--------

Manikandan Muralidharan (3):
  spi: atmel: simplify MR register update in cs_activate()
  spi: dt-bindings: atmel,at91rm9200-spi: Add support for optional
    'spi_gclk' clock
  spi: atmel: Add support for handling GCLK as a clock source

 .../bindings/spi/atmel,at91rm9200-spi.yaml    | 11 ++-
 drivers/spi/spi-atmel.c                       | 78 ++++++++++++++-----
 2 files changed, 66 insertions(+), 23 deletions(-)


base-commit: 7e161a991ea71e6ec526abc8f40c6852ebe3d946
-- 
2.25.1