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X-CSE-ConnectionGUID: 1ukqY7Z2Svu+qnOLrd9exQ== X-CSE-MsgGUID: shrOJ1pbSdyVYGCiC+RoQw== X-IronPort-AV: E=Sophos;i="6.18,230,1751266800"; d="scan'208";a="46483414" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 01 Sep 2025 22:52:45 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 1 Sep 2025 22:52:34 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 1 Sep 2025 22:52:30 -0700 From: Dharma Balasubiramani Date: Tue, 2 Sep 2025 11:22:18 +0530 Subject: [PATCH 1/5] spi: atmel,quadspi: Document sam9x7 QSPI Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20250902-microchip-qspi-v1-1-37af59a0406a@microchip.com> References: <20250902-microchip-qspi-v1-0-37af59a0406a@microchip.com> In-Reply-To: <20250902-microchip-qspi-v1-0-37af59a0406a@microchip.com> To: Mark Brown , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Nicolas Ferre" , Alexandre Belloni , Claudiu Beznea , Tudor Ambarus CC: , , , , Dharma Balasubiramani X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756792344; l=878; i=dharma.b@microchip.com; s=20240209; h=from:subject:message-id; bh=g9qQXv2V8dA8IDQzFPk9fFZ2WneEXRTGvShebfzPtjM=; b=RXLzmMxnP+ToN+Z5oDPtF+Ea94CKvLTLwp5jSikf1MtD2AeOR7+ez1eDz8FFGXArQU76S7HRC HyNXMhbLmr4DKegxye+QNurlMaBOIchdFnsq2nOnOmPZ9VClBFbWItx X-Developer-Key: i=dharma.b@microchip.com; a=ed25519; pk=kCq31LcpLAe9HDfIz9ZJ1U7T+osjOi7OZSbe0gqtyQ4= Document the sam9x75 quad spi that supports interface to serial memories operating in - Single-bit SPI, Dual SPI, Quad SPI and Octal SPI - Single Data Rate or Double Data Rate modes Signed-off-by: Dharma Balasubiramani --- Documentation/devicetree/bindings/spi/atmel,quadspi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml index b0d99bc10535..c17114123034 100644 --- a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml @@ -17,6 +17,7 @@ properties: enum: - atmel,sama5d2-qspi - microchip,sam9x60-qspi + - microchip,sam9x7-ospi - microchip,sama7g5-qspi - microchip,sama7g5-ospi -- 2.43.0