From: Santhosh Kumar K <s-k6@ti.com>
To: <miquel.raynal@bootlin.com>, <broonie@kernel.org>,
<vigneshr@ti.com>, <marex@denx.de>, <computersforpeace@gmail.com>,
<grmoore@opensource.altera.com>, <theo.lebrun@bootlin.com>
Cc: <linux-spi@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<s-k6@ti.com>, <praneeth@ti.com>, <p-mantena@ti.com>,
<a-dutta@ti.com>, <u-kumar1@ti.com>
Subject: [PATCH 3/4] spi: cadence-quadspi: Fix cqspi_setup_flash()
Date: Thu, 4 Sep 2025 19:01:29 +0530 [thread overview]
Message-ID: <20250904133130.3105736-4-s-k6@ti.com> (raw)
In-Reply-To: <20250904133130.3105736-1-s-k6@ti.com>
The 'max_cs' stores the largest chip select number. It should only
be updated when the current 'cs' is greater than existing 'max_cs'. So,
fix the condition accordingly.
Fixes: 0f3841a5e115 ("spi: cadence-qspi: report correct number of chip-select")
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
---
drivers/spi/spi-cadence-quadspi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 447a32a08a93..da3ec15abb3e 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1722,7 +1722,7 @@ static const struct spi_controller_mem_caps cqspi_mem_caps = {
static int cqspi_setup_flash(struct cqspi_st *cqspi)
{
- unsigned int max_cs = cqspi->num_chipselect - 1;
+ unsigned int max_cs = 0;
struct platform_device *pdev = cqspi->pdev;
struct device *dev = &pdev->dev;
struct cqspi_flash_pdata *f_pdata;
@@ -1740,7 +1740,7 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi)
if (cs >= cqspi->num_chipselect) {
dev_err(dev, "Chip select %d out of range.\n", cs);
return -EINVAL;
- } else if (cs < max_cs) {
+ } else if (cs > max_cs) {
max_cs = cs;
}
--
2.34.1
next prev parent reply other threads:[~2025-09-04 13:32 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-04 13:31 [PATCH 0/4] Miscellaneous fixes and clean-ups Santhosh Kumar K
2025-09-04 13:31 ` [PATCH 1/4] spi: cadence-quadspi: Flush posted register writes before INDAC access Santhosh Kumar K
2025-09-04 14:35 ` Pratyush Yadav
2025-09-04 13:31 ` [PATCH 2/4] spi: cadence-quadspi: Flush posted register writes before DAC access Santhosh Kumar K
2025-09-04 14:36 ` Pratyush Yadav
2025-09-04 13:31 ` Santhosh Kumar K [this message]
2025-09-04 14:41 ` [PATCH 3/4] spi: cadence-quadspi: Fix cqspi_setup_flash() Pratyush Yadav
2025-09-05 11:04 ` Santhosh Kumar K
2025-09-04 15:32 ` Théo Lebrun
2025-09-05 11:04 ` Santhosh Kumar K
2025-09-04 13:31 ` [PATCH 4/4] spi: cadence-quadspi: Use BIT() macros where possible Santhosh Kumar K
2025-09-04 14:49 ` Pratyush Yadav
2025-09-05 11:04 ` Santhosh Kumar K
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