Re: [PATCH v4 7/8] dt-bindings: iio: adc: adi,ad4030: Add ADAQ4216 and ADAQ4224

[Conor Dooley <conor@kernel.org>]

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On Thu, Oct 09, 2025 at 07:02:31PM -0300, Marcelo Schmitt wrote:
> On 10/08, Conor Dooley wrote:
> > On Wed, Oct 08, 2025 at 10:51:37AM -0300, Marcelo Schmitt wrote:
> > > ADAQ4216 and ADAQ4224 are similar to AD4030 except that ADAQ devices have a
> > > PGA (programmable gain amplifier) that scales the input signal prior to it
> > > reaching the ADC inputs. The PGA is controlled through a couple of pins (A0
> > > and A1) that set one of four possible signal gain configurations.
> > > 
> > > Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
> > > ---
> > > Change log v3 -> v4
> > > - Now only documenting GPIO setup to control ADAQ PGA pins.
> > > 
> > > Pin strapped/hardwired connections to PGA pins may benefit from a "fixed-gpios"
> > > driver which may (or may not?) use the shared GPIO abstraction layer [1]. I may
> > > propose support for pin-strapped/hardwired connections when I get a working
> > > fixed-gpios implementation.
> > 
> > What is a "fixed-gpio" as compared to a hog, from a dt point of view?
> > Is it purely a software change?
> 
> 
> Short answer:
> 
> I think "fixed-gpio" and gpio-hog would mean the same from dt point of view.
> Yes, it's mainly related to software.

Long answer is wasted on me, what you I just wanted to know if you were
proposing something new on the dt side or just able to use hogs :)
Well, wasted in an official capacity, obviously new features in the
kernel are also interesting to learn about.

Cheers,
Conor.

> 
> 
> Long answer:
> 
> We would like to read the state of a pin from the GPIO client driver. Maybe we
> are already able to read gpio-hog states from client drivers and just didn't
> find out how.
> 
> The idea is to standardize and simplify the dt bindings when peripheral pins can
> either be connected GPIOs or hard-wired to some logic level.
> 
> For the particular example of ADAQ4216, it can have PGA control pins connected
> to GPIOs.
> 
>     +-------------+         +-------------+
>     |     ADC     |         |     HOST    |
>     |             |         |             |
>     |   SPI lines |<=======>| SPI lines   |
>     |             |         |             |
>     |          A0 |<--------| GPIO_A      |
>     |          A1 |<--------| GPIO_B      |
>     +-------------+         +-------------+
> 
> But the pins might instead be hard-wired, like
> 
>     +-------------+         +-------------+
>     |     ADC     |         |     HOST    |
>     |             |         |             |
>     |   SPI lines |<=======>| SPI lines   |
>     |             |         +-------------+
>     |          A0 |<-----+
>     |          A1 |<-----+
>     +-------------+      |
>                         VIO
> 
> or
> 
>     +-------------+         +-------------+
>     |     ADC     |         |     HOST    |
>     |             |         |             |
>     |   SPI lines |<=======>| SPI lines   |
>     |             |         +-------------+
>     |          A0 |<--------- VIO
>     |          A1 |<-----+
>     +-------------+      |
>                         GND
> 
> Or even, possibly, a mix of GPIO and hard-wired.
> 
>     +-------------+         +-------------+
>     |     ADC     |         |     HOST    |
>     |             |         |             |
>     |   SPI lines |<=======>| SPI lines   |
>     |             |         |             |
>     |          A0 |<--------| GPIO_A      |
>     |             |         +-------------+
>     |          A1 |<-----+
>     +-------------+      |
>                         GND
> 
> We have bindings (like adi,ad7191.yaml [1]) describing the hard-wired setups
> with function specific properties. E.g.
>   adi,pga-value:
>     $ref: /schemas/types.yaml#/definitions/uint32
>     description: |
>       Should be present if PGA pins are pin-strapped. Possible values:
>       Gain 1 (PGA1=0, PGA2=0)
>       Gain 8 (PGA1=0, PGA2=1)
>       Gain 64 (PGA1=1, PGA2=0)
>       Gain 128 (PGA1=1, PGA2=1)
>       If defined, pga-gpios must be absent.
>     enum: [1, 8, 64, 128]
> 
> This approach works fine, but it requires documenting device-specific values
> (e.g. gain 1, gain 8, ..., gain X) for each new series of ADCs because each
> each series has different hardware properties.
> 
> Sometimes peripherals have pins with different functions that are also either
> hard-wired or connected to GPIOs (like adi,ad7606.yaml [2] and adi,ad7625.yaml [3]).
> Software wants to know about the state of those pins. When they are connected
> to GPIOs, we can just read the GPIO value. But when the pins are hard-wired,
> we have to set additional dt properties (e.g. adi,pga-value) and then software
> figures out the state of the pins from the value read from dt.
> What we wonder is whether it would be possible to have both the GPIO and
> hard-wired cases described by gpio properties.
> 
> [1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/iio/adc/adi,ad7191.yaml#n77
> [2]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml#n127
> [3]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/iio/adc/adi,ad7625.yaml#n70
> 
> For example, instead of having
> 
> /* All GPIOs case */
> pga-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>, <&gpio 24 GPIO_ACTIVE_HIGH>;
> 
> and
> 
> /* All hard-wired (pin-strapped) case */
> adi,pga-value = <1>;
> 
> maybe we could have something like
> 
> /* All gpios */
> pga-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>,
>             <&gpio0 1 GPIO_ACTIVE_HIGH>;
> /* or all hard-wired */
> pga-gpios = <&fixed_gpio GPIO_FIXED_LOW>,
>             <&fixed_gpio GPIO_FIXED_LOW>;
> 
> as suggested by David [4].
> 
> Though, I'm also a bit worried about such way of describing the hard-wired
> connections being potentially confusing as those "fixed-gpios" would not
> necessarily mean any actual GPIO.
> 
> [4]: https://lore.kernel.org/linux-iio/CAMknhBHzXLjkbKAjkgRwEps=0YrOgUcdvRpuPRrcPkwfwWo88w@mail.gmail.com/
> 
> 
> With best regards,
> Marcelo

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