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Thu, 16 Oct 2025 06:29:27 -0700 From: Vishwaroop A To: Mark Brown , Thierry Reding , Jonathan Hunter , "Sowjanya Komatineni" , Laxman Dewangan , , CC: Vishwaroop A , , , Subject: [PATCH v2 0/2] spi: tegra210-quad: Improve timeout handling under high system load Date: Thu, 16 Oct 2025 13:29:21 +0000 Message-ID: <20251016132923.3577429-1-va@nvidia.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E0:EE_|LV2PR12MB6014:EE_ X-MS-Office365-Filtering-Correlation-Id: b6e85f02-d08f-40b9-1c4d-08de0cb8116f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?FHoE5GA+XJvFbd7fu0KEf/o3WmZTos7/q1gpM+EHpG0vi2EHrchKFum/WgON?= =?us-ascii?Q?g/UhfCn5utiFPxSvXqTVpQjGQ49fiv9kTWU0PBrBoCT6TAOgiD8nRhBPePR8?= =?us-ascii?Q?Y+hWsKNhB5AgsOUSN51ob4olzJj2EAWbLz1aZr8HkkW8UYoH24xO2gvUx10l?= =?us-ascii?Q?pvSiMf0kFUZLb3IAyV71saiJXJNbnRnInAAUa01CgWtCFo9AZ4AyiGSCDudC?= =?us-ascii?Q?98S0GnyobxszngcXzBxz77FMPRhcHFXbkXS59W65eYAnN3M+3VIVr9fSKuvP?= =?us-ascii?Q?wKL0SkDuSMb0rqDWeY+DT8JILa3MAvXlP6+eylIw1ofoikFIssWxoXN9tid5?= =?us-ascii?Q?TIQ/tmzCtE8nDJCToRQocSJYppC1ddmf3wdSU73+VvVAFbrT+l6CtCZ/3eVl?= =?us-ascii?Q?VPK6WIxGSRyLO8de5dGgsebm3sV6K5AIntHF8416Th84wChnWcPsFU/s2WHg?= =?us-ascii?Q?lLdONkw+at3lF8jMtvOxLX4htodIK2Xsr422xT2wMuspJkicrRZoot8ylwY+?= =?us-ascii?Q?WKS2Bb8+Wx3uQIoMxVHQlaG1deeVW24KcWBpgAYdlssKUlSdbKvBk2lpMnY5?= =?us-ascii?Q?sZkgqGos79lTGJpCqE1OqGSAsqLL3d1SiKUrbkJy9H5VnJGwXObqH7Y7u8VT?= =?us-ascii?Q?Ebn+1h8RSJ+E/hOBhhBwCmall9OrtcIXTriPJdGvaYTihBfq/4Jvzfa5iwfz?= =?us-ascii?Q?MvsY/RzbmrmV9ecJQXwQzU4yJaTofpVaZ4hQo2wZYXCE5mJ14e2eCDmHeeYN?= =?us-ascii?Q?xZjBXVtI5itpdXX362ajwVfIdExFwAtsnkwRWWg87XZikVkavEJrGj1k/PNy?= =?us-ascii?Q?vdmZ69Zb6NN+MQN2o9foAL/W3/yUdEdlRQVhj++pWc4ck5+RXVYN65ew2EZH?= =?us-ascii?Q?ycnk8X9powHSG6KOGAHWbVs4KlZIR8cp/MaNL4BpPN/KyF5xkgjc/Io8XvJu?= =?us-ascii?Q?qMiOgPVCAfnoIlaZBKVaq3sxgtYHseHJ4ea9R1k7VzXGyrh7fLFwTKUY+b90?= =?us-ascii?Q?X4poVVuN+T6xDtQd2YTw+NdgkAsKT2SyGvnt5aT4T0fCN1/8EYZAiMAmJ+ws?= =?us-ascii?Q?yc/XnQX5ve2IpXos+4TP2s6hbVbES1hk6JBnFrPC0ndn9EeMJ3euZA4lOsmN?= =?us-ascii?Q?+ITeU/Q3Z+sMpsEVdrsMv/33PkEdsXsF6yuWYptTF6KUrzR3k0xhe64D1wwb?= =?us-ascii?Q?l6ewG6YwuI0D8x1PaTiOCSpkrjBrjKz/XCZVI8ed7dDLhZXjXt+Vjm7Ae594?= =?us-ascii?Q?1mnneiCL+SsgzBYfaizcmmeqHv+vtG4BYuTZwRHgLEa3LODEWuZ2YjBoLixk?= =?us-ascii?Q?nKd52fmPX01NPgcZHAawZRCskiC1Bv07LxKIjOUNGqV0wvAtGssroEpryWOb?= =?us-ascii?Q?Pg2MbidgvHsWStyWKk/kqMbIk+AymzXNzZXcOUz5ddaP2jLXzlJJLemYiu0i?= =?us-ascii?Q?ysTxVeq5Fo1LpzGvqziKnSu4uSO04zTIQD6flggqQ9ElNONb6EqjRm7nwo3a?= =?us-ascii?Q?e9hI9Mp/MSdDoIgBPnbyo6eYt4kmuRB78YSHXZGl1yKXzvSIss90w3EXSvds?= =?us-ascii?Q?RJKNj8CPNaNicLaih0M=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2025 13:29:43.7319 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b6e85f02-d08f-40b9-1c4d-08de0cb8116f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E0.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB6014 Hi, This patch series addresses timeout handling issues in the Tegra QSPI driver that occur under high system load conditions. We've observed that when CPUs are saturated (due to error injection, RAS firmware activity, or general CPU contention), QSPI interrupt handlers can be delayed, causing spurious transfer failures even though the hardware completed the operation successfully. Patch 1 fixes a stale pointer issue by ensuring curr_xfer is cleared on timeout and checked when the IRQ thread finally runs. It also ensures interrupts are properly cleared on failure paths. Patch 2 adds hardware status checking on timeout. Before failing a transfer, the driver now reads QSPI_TRANS_STATUS to verify if the hardware actually completed the operation. If so, it manually invokes the completion handler instead of failing the transfer. This distinguishes genuine hardware timeouts from delayed/lost interrupts. These changes have been tested in production environments under various high load scenarios including RAS testing and CPU saturation workloads. Changes in v2: - Fixed indentation in patch 1/2: The "Reset controller if timeout happens" block now has correct indentation (inside the WARN_ON_ONCE block) - No functional changes Testing: - Verified normal operation under light load - Tested under heavy CPU load with concurrent workloads - Validated with RAS firmware activity and error injection - Confirmed no regressions in existing timeout behavior Thierry Reding (1): spi: tegra210-quad: Fix timeout handling Vishwaroop A (1): spi: tegra210-quad: Check hardware status on timeout drivers/spi/spi-tegra210-quad.c | 195 ++++++++++++++++++++++++++------ 1 file changed, 138 insertions(+), 57 deletions(-) -- 2.34.1