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[75.72.117.212]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-5abb7fdb7c7sm2427824173.44.2025.10.24.12.16.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Oct 2025 12:16:01 -0700 (PDT) From: Alex Elder To: han.xu@nxp.com, broonie@kernel.org Cc: dlan@gentoo.org, Frank.li@nxp.com, guodong@riscstar.com, linux-spi@vger.kernel.org, imx@lists.linux.dev, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Frank Li Subject: [PATCH v3 6/9] spi: fsl-qspi: introduce sfa_size devtype data Date: Fri, 24 Oct 2025 14:15:46 -0500 Message-ID: <20251024191550.194946-7-elder@riscstar.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251024191550.194946-1-elder@riscstar.com> References: <20251024191550.194946-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit In fsl_qspi_default_setup(), four registers define the size of blocks of data to written to each of four chips that comprise SPI NOR flash storage. They are currently defined to be the same as the AHB buffer size. The SpacemiT QSPI has an AHB buffer size of 512 bytes, but requires these four sizes to be multiples of 1024 bytes. Define a new field sfa_size in the fsl_qspi_devtype_data structure that, if non-zero, will be used instead of the AHB buffer size to define the size of these chip regions. Reviewed-by: Frank Li Signed-off-by: Alex Elder --- v3: - The variable used in fsl_qspi_default_setup() is now "sfa_size" - Changed the subject line drivers/spi/spi-fsl-qspi.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c index 2c030dd6facc7..46a3187b33548 100644 --- a/drivers/spi/spi-fsl-qspi.c +++ b/drivers/spi/spi-fsl-qspi.c @@ -207,6 +207,7 @@ struct fsl_qspi_devtype_data { unsigned int txfifo; int invalid_mstrid; unsigned int ahb_buf_size; + unsigned int sfa_size; unsigned int quirks; bool little_endian; }; @@ -737,6 +738,7 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q) { void __iomem *base = q->iobase; u32 reg, addr_offset = 0; + u32 sfa_size; int ret; /* disable and unprepare clock to avoid glitch pass to controller */ @@ -795,17 +797,17 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q) * In HW there can be a maximum of four chips on two buses with * two chip selects on each bus. We use four chip selects in SW * to differentiate between the four chips. - * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD, - * SFB2AD accordingly. + * + * By default we write the AHB buffer size to each chip, but + * a different size can be specified with devtype_data->sfa_size. + * The SFA1AD, SFA2AD, SFB1AD, and SFB2AD registers define the + * top (end) of these four regions. */ - qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset, - base + QUADSPI_SFA1AD); - qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset, - base + QUADSPI_SFA2AD); - qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset, - base + QUADSPI_SFB1AD); - qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset, - base + QUADSPI_SFB2AD); + sfa_size = q->devtype_data->sfa_size ? : q->devtype_data->ahb_buf_size; + qspi_writel(q, addr_offset + 1 * sfa_size, base + QUADSPI_SFA1AD); + qspi_writel(q, addr_offset + 2 * sfa_size, base + QUADSPI_SFA2AD); + qspi_writel(q, addr_offset + 3 * sfa_size, base + QUADSPI_SFB1AD); + qspi_writel(q, addr_offset + 4 * sfa_size, base + QUADSPI_SFB2AD); q->selected = -1; -- 2.48.1