[PATCH v2 0/3] spi-cadence: support transmission with bits_per_word of 16 and 32

[PATCH v2 0/3] spi-cadence: support transmission with bits_per_word of 16 and 32

[Jun Guo]

The Cadence SPI IP supports configurable FIFO data widths during
integration. On some SoCs, the FIFO data width is designed to be 16 or
32 bits at the chip design stage. However, the current driver only
supports communication with an 8-bit FIFO data width. Therefore, these
patches are added to enable the driver to support communication with
16-bit and 32-bit FIFO data widths.

This series introduces the following enhancements for Cadence SPI
controller support on arm64 platforms:

Patch 1: Add a compatible string "cix,sky1-spi-r1p6" for the cix
sky1 SoC.
Patch 2: Update DT binding docs to support cix sky1 SoC.
Patch 3: Enhance the SPI Cadence driver to support data transmission
with bits_per_word values of 16 and 32.

The CIX Sky1 SPI supported patch is added:
https://lore.kernel.org/all/20250919013118.853078-1-jun.guo@cixtech.com/

The patches have been tested on CIX SKY1 platform.

Changes for v2:
- Remove the fifo-width property and add a compatible string for the
  cix sky1 SoC to control the FIFO data width configuration.

Jun Guo (3):
  arm64: dts: cix: add a compatible string for the cix sky1 SoC
  dt-bindings: spi: spi-cadence: update DT binding docs to support cix
    sky1 SoC
  spi: spi-cadence: supports transmission with bits_per_word of 16 and
    32

 .../devicetree/bindings/spi/spi-cadence.yaml  |  11 +-
 arch/arm64/boot/dts/cix/sky1.dtsi             |   4 +-
 drivers/spi/spi-cadence.c                     | 106 +++++++++++++++---
 3 files changed, 103 insertions(+), 18 deletions(-)

-- 
2.34.1

[PATCH v2 1/3] arm64: dts: cix: add a compatible string for the cix sky1 SoC

[Jun Guo]

The SPI IP design for the cix sky1 SoC uses a FIFO with a data width
of 32 bits, instead of the default 8 bits. Therefore, a compatible
string is added to specify the FIFO data width configuration for the
cix sky1 SoC.

Signed-off-by: Jun Guo <jun.guo@cixtech.com>
---
 arch/arm64/boot/dts/cix/sky1.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
index d21387224e79..189b9a3be55c 100644
--- a/arch/arm64/boot/dts/cix/sky1.dtsi
+++ b/arch/arm64/boot/dts/cix/sky1.dtsi
@@ -265,7 +265,7 @@ i2c7: i2c@4080000 {
 		};
 
 		spi0: spi@4090000 {
-			compatible = "cdns,spi-r1p6";
+			compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6";
 			reg = <0x0 0x04090000 0x0 0x10000>;
 			clocks = <&scmi_clk CLK_TREE_FCH_SPI0_APB>,
 				 <&scmi_clk CLK_TREE_FCH_SPI0_APB>;
@@ -275,7 +275,7 @@ spi0: spi@4090000 {
 		};
 
 		spi1: spi@40a0000 {
-			compatible = "cdns,spi-r1p6";
+			compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6";
 			reg = <0x0 0x040a0000 0x0 0x10000>;
 			clocks = <&scmi_clk CLK_TREE_FCH_SPI1_APB>,
 				 <&scmi_clk CLK_TREE_FCH_SPI1_APB>;
-- 
2.34.1

[PATCH v2 2/3] dt-bindings: spi: spi-cadence: update DT binding docs to support cix sky1 SoC

[Jun Guo]

- Add new compatible strings to the DT binding documents to support
 cix sky1 SoC;
- Adjust the configuration of the compatible property to support both
 single-item and two-items cases.​​

Signed-off-by: Jun Guo <jun.guo@cixtech.com>
---
 .../devicetree/bindings/spi/spi-cadence.yaml          | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-cadence.yaml b/Documentation/devicetree/bindings/spi/spi-cadence.yaml
index 8de96abe9da1..e75b142a1368 100644
--- a/Documentation/devicetree/bindings/spi/spi-cadence.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-cadence.yaml
@@ -14,9 +14,14 @@ allOf:
 
 properties:
   compatible:
-    enum:
-      - cdns,spi-r1p6
-      - xlnx,zynq-spi-r1p6
+    oneOf:
+      - enum:
+          - cdns,spi-r1p6
+          - xlnx,zynq-spi-r1p6
+      - items:
+          - enum:
+              - cix,sky1-spi-r1p6
+          - const: cdns,spi-r1p6
 
   reg:
     maxItems: 1
-- 
2.34.1

Re: [PATCH v2 2/3] dt-bindings: spi: spi-cadence: update DT binding docs to support cix sky1 SoC

[Conor Dooley]

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On Mon, Oct 27, 2025 at 04:42:38PM +0800, Jun Guo wrote:
> - Add new compatible strings to the DT binding documents to support
>  cix sky1 SoC;
> - Adjust the configuration of the compatible property to support both
>  single-item and two-items cases.​​
> 
> Signed-off-by: Jun Guo <jun.guo@cixtech.com>
> ---
>  .../devicetree/bindings/spi/spi-cadence.yaml          | 11 ++++++++---
>  1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/spi/spi-cadence.yaml b/Documentation/devicetree/bindings/spi/spi-cadence.yaml
> index 8de96abe9da1..e75b142a1368 100644
> --- a/Documentation/devicetree/bindings/spi/spi-cadence.yaml
> +++ b/Documentation/devicetree/bindings/spi/spi-cadence.yaml
> @@ -14,9 +14,14 @@ allOf:
>  
>  properties:
>    compatible:
> -    enum:
> -      - cdns,spi-r1p6
> -      - xlnx,zynq-spi-r1p6
> +    oneOf:
> +      - enum:
> +          - cdns,spi-r1p6
> +          - xlnx,zynq-spi-r1p6
> +      - items:
> +          - enum:
> +              - cix,sky1-spi-r1p6
> +          - const: cdns,spi-r1p6

This doesn't apply, probably needs a rebase on spi/for-next?
Approach is correct though, but it'll be a more minimal patch when
rebased.
pw-bot: changes-requested

>  
>    reg:
>      maxItems: 1
> -- 
> 2.34.1
> 

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Re: [PATCH v2 2/3] dt-bindings: spi: spi-cadence: update DT binding docs to support cix sky1 SoC

[Jun Guo]

Hi Conor,

​Thank you for your prompt feedback.​​

On 10/28/2025 12:51 AM, Conor Dooley wrote:
> On Mon, Oct 27, 2025 at 04:42:38PM +0800, Jun Guo wrote:
>> - Add new compatible strings to the DT binding documents to support
>>   cix sky1 SoC;
>> - Adjust the configuration of the compatible property to support both
>>   single-item and two-items cases.​​
>>
>> Signed-off-by: Jun Guo<jun.guo@cixtech.com>
>> ---
>>   .../devicetree/bindings/spi/spi-cadence.yaml          | 11 ++++++++---
>>   1 file changed, 8 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/spi/spi-cadence.yaml b/Documentation/devicetree/bindings/spi/spi-cadence.yaml
>> index 8de96abe9da1..e75b142a1368 100644
>> --- a/Documentation/devicetree/bindings/spi/spi-cadence.yaml
>> +++ b/Documentation/devicetree/bindings/spi/spi-cadence.yaml
>> @@ -14,9 +14,14 @@ allOf:
>>   
>>   properties:
>>     compatible:
>> -    enum:
>> -      - cdns,spi-r1p6
>> -      - xlnx,zynq-spi-r1p6
>> +    oneOf:
>> +      - enum:
>> +          - cdns,spi-r1p6
>> +          - xlnx,zynq-spi-r1p6
>> +      - items:
>> +          - enum:
>> +              - cix,sky1-spi-r1p6
>> +          - const: cdns,spi-r1p6
> This doesn't apply, probably needs a rebase on spi/for-next?
> Approach is correct though, but it'll be a more minimal patch when
> rebased.
> pw-bot: changes-requested
> 
Thank you for the heads-up. I've just seen your patch, and I will base 
my PATCH v3 on top of it.>>
>>     reg:
>>       maxItems: 1
>> -- 
>> 2.34.1

[PATCH v2 3/3] spi: spi-cadence: supports transmission with bits_per_word of 16 and 32

[Jun Guo]

The default FIFO data width of the Cadence SPI IP is 8 bits, but
the hardware supports configurations of 16 bits and 32 bits.
This patch enhances the driver to support communication with both
16-bits and 32-bits FIFO data widths.

Signed-off-by: Jun Guo <jun.guo@cixtech.com>
---
 drivers/spi/spi-cadence.c | 106 +++++++++++++++++++++++++++++++++-----
 1 file changed, 93 insertions(+), 13 deletions(-)

diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
index 5ae09b21d23a..47054da630d0 100644
--- a/drivers/spi/spi-cadence.c
+++ b/drivers/spi/spi-cadence.c
@@ -109,6 +109,7 @@
  * @rxbuf:		Pointer to the RX buffer
  * @tx_bytes:		Number of bytes left to transfer
  * @rx_bytes:		Number of bytes requested
+ * @n_bytes:		Number of bytes per word
  * @dev_busy:		Device busy flag
  * @is_decoded_cs:	Flag for decoder property set or not
  * @tx_fifo_depth:	Depth of the TX FIFO
@@ -120,16 +121,24 @@ struct cdns_spi {
 	struct clk *pclk;
 	unsigned int clk_rate;
 	u32 speed_hz;
-	const u8 *txbuf;
-	u8 *rxbuf;
+	const void *txbuf;
+	void *rxbuf;
 	int tx_bytes;
 	int rx_bytes;
+	u8 n_bytes;
 	u8 dev_busy;
 	u32 is_decoded_cs;
 	unsigned int tx_fifo_depth;
 	struct reset_control *rstc;
 };
 
+enum cdns_spi_frame_n_bytes {
+	CDNS_SPI_N_BYTES_NULL = 0,
+	CDNS_SPI_N_BYTES_U8 = 1,
+	CDNS_SPI_N_BYTES_U16 = 2,
+	CDNS_SPI_N_BYTES_U32 = 4
+};
+
 /* Macros for the SPI controller read/write */
 static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
 {
@@ -305,6 +314,78 @@ static int cdns_spi_setup_transfer(struct spi_device *spi,
 	return 0;
 }
 
+static u8 cdns_spi_n_bytes(struct spi_transfer *transfer)
+{
+	if (transfer->bits_per_word <= 8)
+		return CDNS_SPI_N_BYTES_U8;
+	else if (transfer->bits_per_word <= 16)
+		return CDNS_SPI_N_BYTES_U16;
+	else
+		return CDNS_SPI_N_BYTES_U32;
+}
+
+static inline void cdns_spi_reader(struct cdns_spi *xspi)
+{
+	u32 rxw = 0;
+
+	if (xspi->rxbuf && !IS_ALIGNED((uintptr_t)xspi->rxbuf, xspi->n_bytes)) {
+		pr_err("%s: rxbuf address is not aligned for %d bytes\n",
+		       __func__, xspi->n_bytes);
+		return;
+	}
+
+	rxw = cdns_spi_read(xspi, CDNS_SPI_RXD);
+	if (xspi->rxbuf) {
+		switch (xspi->n_bytes) {
+		case CDNS_SPI_N_BYTES_U8:
+			*(u8 *)xspi->rxbuf = rxw;
+			break;
+		case CDNS_SPI_N_BYTES_U16:
+			*(u16 *)xspi->rxbuf = rxw;
+			break;
+		case CDNS_SPI_N_BYTES_U32:
+			*(u32 *)xspi->rxbuf = rxw;
+			break;
+		default:
+			pr_err("%s invalid n_bytes %d\n", __func__,
+			       xspi->n_bytes);
+			return;
+		}
+		xspi->rxbuf = (u8 *)xspi->rxbuf + xspi->n_bytes;
+	}
+}
+
+static inline void cdns_spi_writer(struct cdns_spi *xspi)
+{
+	u32 txw = 0;
+
+	if (xspi->txbuf && !IS_ALIGNED((uintptr_t)xspi->txbuf, xspi->n_bytes)) {
+		pr_err("%s: txbuf address is not aligned for %d bytes\n",
+		       __func__, xspi->n_bytes);
+		return;
+	}
+
+	if (xspi->txbuf) {
+		switch (xspi->n_bytes) {
+		case CDNS_SPI_N_BYTES_U8:
+			txw = *(u8 *)xspi->txbuf;
+			break;
+		case CDNS_SPI_N_BYTES_U16:
+			txw = *(u16 *)xspi->txbuf;
+			break;
+		case CDNS_SPI_N_BYTES_U32:
+			txw = *(u32 *)xspi->txbuf;
+			break;
+		default:
+			pr_err("%s invalid n_bytes %d\n", __func__,
+			       xspi->n_bytes);
+			return;
+		}
+		cdns_spi_write(xspi, CDNS_SPI_TXD, txw);
+		xspi->txbuf = (u8 *)xspi->txbuf + xspi->n_bytes;
+	}
+}
+
 /**
  * cdns_spi_process_fifo - Fills the TX FIFO, and drain the RX FIFO
  * @xspi:	Pointer to the cdns_spi structure
@@ -321,23 +402,14 @@ static void cdns_spi_process_fifo(struct cdns_spi *xspi, int ntx, int nrx)
 
 	while (ntx || nrx) {
 		if (nrx) {
-			u8 data = cdns_spi_read(xspi, CDNS_SPI_RXD);
-
-			if (xspi->rxbuf)
-				*xspi->rxbuf++ = data;
-
+			cdns_spi_reader(xspi);
 			nrx--;
 		}
 
 		if (ntx) {
-			if (xspi->txbuf)
-				cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
-			else
-				cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
-
+			cdns_spi_writer(xspi);
 			ntx--;
 		}
-
 	}
 }
 
@@ -454,6 +526,10 @@ static int cdns_transfer_one(struct spi_controller *ctlr,
 	if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL)
 		udelay(10);
 
+	xspi->n_bytes = cdns_spi_n_bytes(transfer);
+	xspi->tx_bytes = DIV_ROUND_UP(xspi->tx_bytes, xspi->n_bytes);
+	xspi->rx_bytes = DIV_ROUND_UP(xspi->rx_bytes, xspi->n_bytes);
+
 	cdns_spi_process_fifo(xspi, xspi->tx_fifo_depth, 0);
 
 	cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
@@ -654,6 +730,9 @@ static int cdns_spi_probe(struct platform_device *pdev)
 	ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
 	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
 
+	if (of_device_is_compatible(pdev->dev.of_node, "cix,sky1-spi-r1p6"))
+		ctlr->bits_per_word_mask |= SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
+
 	if (!spi_controller_is_target(ctlr)) {
 		ctlr->mode_bits |=  SPI_CS_HIGH;
 		ctlr->set_cs = cdns_spi_chipselect;
@@ -797,6 +876,7 @@ static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
 
 static const struct of_device_id cdns_spi_of_match[] = {
 	{ .compatible = "xlnx,zynq-spi-r1p6" },
+	{ .compatible = "cix,sky1-spi-r1p6" },
 	{ .compatible = "cdns,spi-r1p6" },
 	{ /* end of table */ }
 };
-- 
2.34.1